Leaving California for the first time, the 12th annual IEEE International Interconnect Technology Conference (IITC) will take place in Sapporo, Japan, June 1-3. With lithographic shrinks in 2D dimensions slowing, interconnects between chips in packages and in 3D stacks will be the driver for increased density and functionality in ICs. Thus, the more than 80 […]
Researchers at MIT have demonstrated deep subwavelength lithography using a photochromic contrast enhancing layer, as reported in SciencExpress April 9. A thin photochromic film on top of a conventional photoresist layer was exposed to two wavelengths of light with two distinct patterns. One wavelength exposed the photoresist while the other made the photochromic film opaque […]
IMEC has successfully transferred memory variability aware modeling (MemoryVAM), the first EDA tool for statistical memory analysis, to Samsung Electronics. The tool predicts yield loss of embedded SRAMs caused by the process variations of deep-submicron IC technologies. This may be the first proven design-for-manufacturing (DFM) tool to provide statistical analysis across degrees of abstraction from […]
The Materials Research Society (MRS) Spring Meeting in San Francisco is so huge, this year attracting a record of over 5,000 attendees, that strategy is needed to try to see any representative sample of the event. To provide in-depth information about new materials technologies, new symposia have been added over the years such that there […]
On April 7, 2009, KLA-Tencor introduced the TeraScanXR, the latest version of their TeraScan reticle inspection system, this one intended for 32nm node DUV masks. This new tool, an extension of existing reticle inspection systems, is designed to provide mask manufacturers better sensitivity, lower cost-per-inspection and faster mask dispositioning. Improvements in overall sensitivity in die-to-die […]
The SPIE Europe Microtechnologies For the New Millennium congress has new partners this year, with the involvement of GMM, the Society of Microelectronics, Micro and Precision Engineering and the magazine mst|news as Cooperating Organisations for the first time. The event will be held at the Congress Centre Maritim Hotel in Dresden, Germany, 4-6 May 2009. […]
The control of complex interdependencies is critical for the successful manufacturing of nanometer-scale ICs. Every aspect of every unit process step in the line must be ever more tightly controlled to ensure that 45nm and 32nm node chips can be made with good yield. To serve the market, Novellus continues to announce new integrated surface-treatment […]
German and French teams are combining EUR 14.5m investment into development of strained-silicon on insulator (sSOI) technology under the DEvice and CIrcuit performance boosted through SIlicon material Fabrication (DECISIF) program. The work will combine original research results from Research Center Juelich and Leti/Soitec to try to lower costs and defect-densities in the creation of 300mm […]
Novellus’ applications labs have been working on CVD low-k dielectrics targeting 32nm node multilevel metal specs, and the result is “dense” ultra-low-k (ULK) film with bulk k=2.5 and the potential to go lower. Combined with the company’s multi-station sequential processing (MSSP) tool architecture for the barrier/cap depositions and UV/thermal cure steps, the result is a […]
Nanometrics today announced the release of Version 2.0 of its NanoCD Suite of solutions for optical critical dimension (OCD) metrology, just one year after V1 was released. OCD (a.k.a., “scatterometry”) has been used to successfully control fab processes for many years. The major known limitation of the technique is model building from reference metrology data, […]