Posts Tagged ‘45nm’

Friday, March 20th, 2009

Novellus’ applications labs have been working on CVD low-k dielectrics targeting 32nm node multilevel metal specs, and the result is “dense” ultra-low-k (ULK) film with bulk k=2.5 and the potential to go lower. Combined with the company’s multi-station sequential processing (MSSP) tool architecture for the barrier/cap depositions and UV/thermal cure steps, the result is a […]

Thursday, March 19th, 2009

Mentor Graphics has announced new capabilities to the Calibre(R) platform to allow designers to control thickness variability due to Chemical Mechanical Planarization (CMP) at advanced process nodes. Designers can transition from dummy fill to density-based fill, or to full model-based fill, depending on the demands of their designs and target manufacturing process. The new capability […]

Wednesday, March 4th, 2009

Electron beam direct write (EBDW) lithography is well-developed and has better potential resolution than any other method, but writing speeds did not keep up with Moore’s law after about 1980, leading to abysmal throughput (measured in hours per wafer). Now, the e-Beam Initiative focusing on design for e-beam manufacturing (DFEB) and multibeam writing using MEMS […]

Tuesday, March 3rd, 2009

IEDM 2008 included the unveiling of Schiltron’s (Session 34.6) revolutionary 3-D high density Flash technology that combines the smallest TFTs to date in series strings of up to 64 cells. The unique architecture effectively removes pass disturbs allowing large worst-case string currents and resulting in thinner tunnel oxides, lower erase voltages, and higher endurance than […]

Monday, March 2nd, 2009

Partners SII NanoTechnology and Carl Zeiss NTS have joined with ASML R&D and Toshiba’s process and manufacturing engineering groups to show a new way to create accurate cross-sections of soft photoresist and low-k dielectric lines in dense circuit patterns. First shown in a poster paper at SPIE last week was the ability to generate accurate […]

Monday, February 23rd, 2009

JEOL will install the first e-beam direct-write-on-wafer (EBDW) lithography tool to support nanotechnology development in the Pacific Northwest when the University of Washington takes delivery of a JBX-6300FS tool. The system will be installed in the state-funded Washington Technology Center Microfabrication Lab. Funding for the tool acquisition was provided through a state-supported STAR researchers’ grant […]

Tuesday, February 17th, 2009

Metrosol has joined SEMATECH’s Front End Process Technologies Program at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany to address metrology and data-analysis solutions for 45nm node and beyond IC fabs. The joint partnership will expand on current work to develop inline metrology techniques to monitor the thickness and composition […]

Wednesday, February 11th, 2009

At Levitronix’s Ultrapure Fluid Handling and Wafer Cleaning Conference on February 11th, Particle Measuring Systems reviewed the limits of being able to detect things we do not want to find in flowing fluids, as enabled by a new digital detector array they call NanoVision Technology. Steven Verhaverbeke, tool design expert for Applied Materials who presented […]

Monday, January 26th, 2009

CEA/Leti, along with e-beam lithography supplier Vistec, and new design and software company D2S, recently announced a collaboration focused on refining and validating advanced design-for-e-beam (DFEB) solutions for 45nm and 32nm nodes. Over the next 12 months, Leti will manufacture test chips using a combination of D2S’ design and software capabilities along with the latest […]