{"id":1142,"date":"2010-09-23T22:43:20","date_gmt":"2010-09-24T05:43:20","guid":{"rendered":"http:\/\/www.betasights.net\/wordpress\/?p=1142"},"modified":"2010-09-23T23:33:31","modified_gmt":"2010-09-24T06:33:31","slug":"tsv-ready-in-interposers-at-otaps","status":"publish","type":"post","link":"http:\/\/www.betasights.net\/wordpress\/?p=1142","title":{"rendered":"TSV ready in interposers at OTAPs"},"content":{"rendered":"

Through-silicon vias (TSV) have been in R&D for over 10 years, and finally may reach commercial use in IC manufacturing next year. However, instead of forming vias through silicon in ICs (TSV-IC), the near-term needs will be for vias though silicon interposers (TSV-interposer) made in outsourced test assembly and packaging (OTAP) fabs. Presentations at conferences including SEMICON\/West, IMAPS, and IEDM in this year provide perspective on the slow evolution of this 3D IC technology.<\/span><\/p>\n

\"\"<\/a>TSV has been a bit of a \u201csolution looking for a problem\u201d since first conceived. This editor worked on the technology in the years 1999-2000 for a startup called TruSi<\/a> (now a TSV-interposer foundry called AllVia<\/a>, to which this editor has no relationship<\/em>), trying to sell an atmospheric pressure etch tool to do silicon thinning to 50\u00b5m<\/span> (figure<\/em>) and below. Despite continued interest in TSV capabilities, a viable (pun intended) \u201cproblem\u201d was always lacking. Nonetheless, the entire industry ecosystem of original equipment manufacturers (OEM), specialty materials suppliers (SMS), and consortia have continued to develop and push TSV technologies out into the world. In addition, there have always been \u201cboutique\u201d mil\/aero companies like Vertical Circuits<\/a> with 3D-IC IP looking to expand into high-volume commercial markets. The result is a confusion of options, and no real cost or yield data for volume manufacturing.<\/span><\/p>\n

Perpetual pundit Phil Garrou\u2014now blogging for PennWell’s \u201cElectroIQ\u201d site<\/a> after being tossed out with other editors when Reed closed Semiconductor International\u2014reports that leading OSAT ASE is soon going to be ready with TSV-interposers. During OEM <\/span><\/span>Suss Microtec<\/span><\/span><\/strong>‘s “<\/span><\/span>3D IC Bonding and Thinned Wafer Handling Workshop<\/span><\/span><\/strong>,” at SEMICON\/West this year, Calvin Cheung, vice president of engineering for <\/span><\/span>ASE<\/span><\/span><\/strong>, said, “We currently need an interposer to bond 28nm low-<\/span><\/span>k<\/span><\/span><\/span><\/em> die,” he said. “Right now it is impossible to stack these mechanically unstable materials into a reliable 3D stack in any other way.”<\/span><\/span><\/p>\n

Alchimer<\/span><\/span><\/strong><\/a> also held a workshop at SEMICON\/West to show how it’s all-wet molecular deposition technology can reduce costs in any TSV fill step. During this workshop, Riko Radojcic, director of engineering at <\/span><\/span>Qualcomm<\/span><\/span><\/strong> CDMA Technologies, said that, \u201cWe have certain form-factor constraints that may motivate us to use TSV.\u201d The killer-app is video processing bandwidth in mobile devices, and, \u201cif it will be 3D based on TSV or PoP remains to be seen…but it’s clearly not going to be served by routing through a PCB,\u201d said Radojcic. For Qualcomm’s 3D circuits, the logic chip would be on the bottom with TSV-IC, while memory or analog would be on top as a flip-chip. \u201cWe focus on heterogeneous integration,\u201d explained Radojcic, \u201cnot logic on logic stacking.\u201d Qualcomm’s 3D stacks already have to manage power for other reasons, so any eventual TSV-IC would not need thermal vias.<\/span><\/span><\/p>\n

\"(IEDM<\/a>

(IEDM 2010, Session 35.1)<\/p><\/div>\n

The IMAPS 2010<\/a> conference scheduled for November 2-4 this year in Raleigh, North Carolina will include a special track on 3D packaging and integration [NOTE: early registration and hotel deadline Sept. 24<\/span><\/strong>]. One presentation will be on \u201cEnabling robust copper fill of super high aspect ratio through silicon vias\u201d by Novellus Systems. In an exclusive interview with BetaSights, Novellus’ senior director of business development for 3D applications Damo Srinivas confirmed that interposers appear to be the main near-term TSV volume, and so the final silicon target thickness will be 100-140\u00b5m.<\/span><\/span><\/p>\n

Interposer thickness cannot be reduced below 100 microns without rigid silicon wafers becoming flexible silicon foils. Typical TSV processes to date have worked with 5:1 to 10:1 AR, which may be acceptable for TSV-IC that could be 10-50\u00b5m thick. However, 10-20\u00b5m diameter TSV consume too much silicon area, and take too long to etch and fill. Novellus has integrated a low-temperature vapor deposited dielectric, Cu barrier\/seed vapor deposition, Cu electroplating, and Cu overburden wet-etchback in 20:1 AR TSV 100\u00b5m deep. Novellus has also claimed that proper integration of the barrier\/seed and ECD steps allows for control of the Cu grain orientation inside TSV, such that post-anneal protrusion can be reduced from 0.8 to 0.2 \u00b5m, and at IEDM 2008 protrusion was shown by IBM to increase contact resistance<\/span><\/span>.<\/span><\/span><\/p>\n

\n

TechSearch International<\/a><\/span><\/span> has recently published a market forecast for silicon interposers, as part of the company’s Advanced Packaging Update Service.<\/span><\/span><\/p>\n

\n
Some day the world will probably need TSV-IC for mainstream commercial chips. To that end, the 56th International Electron Devices Meeting (IEDM 2010)<\/a> in San Francisco, California, December 6-8, will include a presentation on TSV-IC titled, \u201cInvestigation on TSV impact on 65nm CMOS devices \tand circuits.\u201d French researchers put 4\u00b5m diameter TSV through \t65nm node ICs (figure<\/em>), and for the first time experimentally quantified an \telectrical coupling between TSVs and MOSFETs. This coupling induced \ta spike variation of up to 7 \u00b5A\/\u00b5m on the static NMOS drain current, though ring oscillators nearby were reportedly not effected. \u2013<\/span><\/span>E.K.<\/span><\/em><\/span><\/dt>\n<\/dl>\n","protected":false},"excerpt":{"rendered":"

TSV for 3D integration of heterogeneous ICs used in interposers first, as shown at SEMICON\/West, IMAPS, IEDM and companies like ASE, Alchimer, Suss, EVG, Novellus, Vertical Circuits, and IBM.<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[9,3,4,10,6,8,11],"tags":[78,354,173,308,15,466,352,353,355,357,130,356,135],"class_list":["post-1142","post","type-post","status-publish","format-standard","hentry","category-equipment","category-manufacturing-fabrication-line","category-integrated-circuit","category-material","category-micro-electro-mechanical-system","category-market-segment","category-service","tag-3d","tag-ase","tag-cu","tag-ecd","tag-etch","tag-integrated-circuit","tag-iedm","tag-imaps","tag-novellus","tag-otap","tag-pvd","tag-qualcomm","tag-tsv"],"_links":{"self":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1142","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1142"}],"version-history":[{"count":23,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1142\/revisions"}],"predecessor-version":[{"id":1154,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1142\/revisions\/1154"}],"wp:attachment":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1142"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1142"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1142"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}