{"id":1177,"date":"2010-10-18T20:27:59","date_gmt":"2010-10-19T03:27:59","guid":{"rendered":"http:\/\/www.betasights.net\/wordpress\/?p=1177"},"modified":"2010-10-18T20:34:39","modified_gmt":"2010-10-19T03:34:39","slug":"iedm-to-show-22nm-alt-channels-and-dual-and-tri-gates","status":"publish","type":"post","link":"http:\/\/www.betasights.net\/wordpress\/?p=1177","title":{"rendered":"IEDM to show 22nm alt-channels and dual- and tri-gates"},"content":{"rendered":"

The International Electronic Devices Meeting (IEDM)<\/a> this year\u2014the 56th<\/span><\/sup> annual meeting, to be held December 6-8, 2010 at the Hilton San Francisco Union Square\u2014will include presentations on alternate channels and multiple gates for CMOS transistors at the upcoming 22nm node. While dual- and tri-gate CMOS transistor devices have been shown for many years, proven single-gate silicon technology has been extended with strain and high-k metal-gate (HKMG) options. Now, with transistor structures such as HKMG reduced to single atomic layers, the next performance boost will likely come with alternate channel materials and the possible use of dual-planar gates.<\/span><\/p>\n

\"A<\/a>

A team led by University of Tokyo wafer-bonded InGaAs alternative channel material to silicon to form dual-gate MOSFETs on an insulating substrate. (Source: IEDM 2010)<\/p><\/div>\n

The limits of the single-gate bulk silicon CMOS transistor seem to be upon us, despite extensive use of strain and other clever extension tricks. For 22nm node devices, there is excessive variability due to channel doping variations (<100 dopants atoms per channel), gate leakage, and parasitic capacitances. Such issues have been known for years, and researchers have developed various known ways forward, including the use of a silicon-on-insulator (SOI), alternate materials for the channels such as germanium (Ge) and indium-gallium-arsenide (InGaAs, figure<\/em>), as well as dual- and tri-gate transistors.<\/p>\n

So far, SOI has been used by IBM and AMD for microprocessors and by all video game makers for the main brains in their boxes, but there is major additional cost for the substrate and so most commercial fabs do not run SOI wafers. Multiple gates have been pushed out again and again. Trigate transistors\u2014a.k.a. \u201cfinFETs\u201d and many variant names for their cross-sectional shapes\u2014have long offered superior performance for minimal additional cost, but EDA models didn’t exist for such devices and so it was difficult to design them into commercial ICs. Now these technologies are under consideration for high-volume use in the next few years, as will be shown in presentations at IEDM 2010.<\/p>\n

Fully-depleted SOI (FDSOI)<\/strong> is claimed by CEA\/Leti\/Minatec [Session 3.2] to be easier to integrate than non-planar devices like finFETs. This paper will address electrostatic integrity, drivability, within wafer variability, and scalability with silicon data down to 18nm gate lengths. Solutions to the challenge of multiple VT<\/sub> transistors and non-logic devices (ESD, I\/Os) will also be reported.<\/p>\n

Dual-gate FDSOI<\/strong> work-function control to tune multiple VT<\/sub> levels will be shown by CEA\/Leti\/Minatec along with ST, Soitec, and Aixtron [Session 3.4]. By work-function engineering of TiN\/TaAlN metal gates, short channel performance of 500\u00b5A\/?m ION and 245?A\/?m IEFF at 2nA\/?m IOFF<\/sub> and VDD<\/sub>=0.9V will be reported on pMOS with a TaAlN gate. The combination of two metal gates with either n- or p-doped ground planes below the Ultra-Thin Buried Oxide (UTBOX) can offer 4 different VT<\/sub> from 0.32V to 0.6V for both nMOS and pMOS. Most of the same researchers will later show [Session 11.2] high-performance planar multi-gates devices with a Si-conduction channel of 4nm, allowing drive current up to 1350\u00b5A\/\u00b5m @Ioff<\/sub>=0.4nA\/\u00b5m. Vitally, this paper will also show how to self-align the two planar gates, based on, \u201cthe direct exposure of a HSQ layer through a 5nm Si-channel.\u201d This opens the way to an easy planar multi-gate process for ultimate CMOS, fully co-integrable with conventional devices.<\/p>\n

\"SEM<\/a>

SEM cross-section of finFET from TSMC's complete high-performance 22\/20nm CMOS logic technology, featuring SiGe stressors, metal gates, and high-k dielectrics. The FinFETs were used to build a dense 0.1\u00b5m2 SRAM memory cell. (Source: IEDM 2010) <\/p><\/div>\n

FinFET<\/strong> architectures will be shown twice by TSMC to be ready for 22nm node fabrication [Sessions 27.1, 34.1]. The company will present on a high performance 22nm bulk finFET (figure<\/em>) that achieve \u201cbest-in-class\u201d Ion of 1200(N)\/1100(P) uA\/um for Ioff=100nA\/\u00b5m at 1V. Dual-Epitaxy and multi-stressors are essential to boost the performance of dual workfunction HKMG transistors. The company’s abstract claims that finFETs, \u201cthe transistor architecture of choice for high performance CPU applications, can also be extended for general purpose SoC applications by proper device optimization.\u201d For low-operating power applications, significant Ion improvement and Ioff reduction are claimed through EOT scaling and mobility improvement. N-finFET and P-finFET achieve ION of 1325 \u00b5A\/\u00b5m and 1000 \u00b5A\/um at 1 nA\/um leakage current under VDD<\/sub> of 1 V, respectively.<\/p>\n

Due to ever increasing complexity and cost, the real details of next-generation fab processes are generally kept secret. Even when discussed, there is always the possibility that the information presented is a dead-end with hidden problems. Novel technology may work, but may come with unacceptable side-effects like cost increases and yield losses. Managing the complexity of process technology interactions, and knowing which processes to deploy at the right time establishes the typically slow pace of evolution.<\/p>\n

So finFETs remain attractive but are probably more challenging to integrate compared to alternate channel materials, and unless TSMC has made a big hidden investment in EDA modeling they probably cannot be designed into mainstream 22nm node ICs. Planar dual-gates are probably the best bet for the next major transistor architecture, so long as a self-aligned approach can be made to yield well. However, even dual-gates may be pushed out past 22nm, since alternate channel materials will likely be used at 22nm and should provide sufficient performance. If so, then the 16nm node would be the first use of dual-gates with or without FDSOI, and finFETs would be pushed out indefinitely.<\/p>\n

The best way to understand this complexity is to attend IEDM and talk to the manufacturing folks who have to make it happen one way or the other. If you cannot attend in person, the conference organizers have created a page on Facebook<\/a>, and they will be posting tweets to Twitter<\/a> including paper titles and links to the technical program sessions. IEDM also includes the latest and greatest presentations on power electronics, memory cells such as Flash and upcoming ReRAM, RF and ultrafast ICs, CMOS image sensors (CIS), and devices results using everybody’s current favorite sticky-tape-your-way-to-a-Nobel-Prize-material<\/a> graphene. A plenary talk entitled \u201c<\/span>Energy Efficiency Enabled by Power Electronics\u201d will be given on the first day by Arunjai Mittal of Infineon Technologies. <\/span>Stay tuned. \u2013<\/span>E.K.<\/em><\/p>\n","protected":false},"excerpt":{"rendered":"

IEDM 2010 best hints at 22nm node fab tech alternate-channel materials, dual- and tri-gate transistors, and RF, MEMS, lab-on-chip, graphene, analog, memory ReRAM results.<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[3,4,10,6,8,11],"tags":[197,362,363,36,324,322,209,111,466,352,366,348,97,468,365,104,141,238,360,361,364],"class_list":["post-1177","post","type-post","status-publish","format-standard","hentry","category-manufacturing-fabrication-line","category-integrated-circuit","category-material","category-micro-electro-mechanical-system","category-market-segment","category-service","tag-22nm","tag-analog","tag-cealeti","tag-cmos","tag-dual-gate","tag-fdsoi","tag-finfet","tag-graphene","tag-integrated-circuit","tag-iedm","tag-infineon","tag-intel","tag-memory","tag-micro-electro-mechanical-system","tag-mittal","tag-reram","tag-rf","tag-soi","tag-transistor","tag-tri-gate","tag-tsmc"],"_links":{"self":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1177","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1177"}],"version-history":[{"count":9,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1177\/revisions"}],"predecessor-version":[{"id":1187,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/1177\/revisions\/1187"}],"wp:attachment":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1177"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=1177"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=1177"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}