{"id":15,"date":"2009-01-05T15:28:34","date_gmt":"2009-01-05T23:28:34","guid":{"rendered":"http:\/\/betasights.net\/wordpress\/?p=15"},"modified":"2009-01-09T00:18:34","modified_gmt":"2009-01-09T08:18:34","slug":"fsi-cleaning-tool-exits-beta-with-payment","status":"publish","type":"post","link":"http:\/\/www.betasights.net\/wordpress\/?p=15","title":{"rendered":"FSI cleaning tool exits beta with payment"},"content":{"rendered":"<div id=\"attachment_19\" style=\"width: 183px\" class=\"wp-caption alignright\"><a href=\"http:\/\/betasights.net\/wordpress\/wp-content\/uploads\/2009\/01\/fsi_orion.gif\"><img loading=\"lazy\" decoding=\"async\" aria-describedby=\"caption-attachment-19\" class=\"size-full wp-image-19\" title=\"fsi_orion\" src=\"http:\/\/betasights.net\/wordpress\/wp-content\/uploads\/2009\/01\/fsi_orion.gif\" alt=\"FSI ORION single-wafer clean tool\" width=\"173\" height=\"202\" \/><\/a><p id=\"caption-attachment-19\" class=\"wp-caption-text\">FSI ORION modular single-wafer cleaning tool<\/p><\/div>\n<p><a href=\"http:\/\/www.fsi-intl.com\/\" target=\"_blank\">FSI International, Inc. <\/a>(Nasdaq: FSII) announced December 23, 2008 that it has received an order for it\u2019s new ORION\u00ae single wafer cleaning platform after a beta evaluation by a major semiconductor manufacturer. The tool will be used for resist strip in 32nm metal interconnect modules, using FSI\u2019s proprietary \u201cViPR\u201d extension of <a href=\"http:\/\/en.wikipedia.org\/wiki\/Piranha_solution\" target=\"_blank\">the classic \u201cpiranha\u201d (a.k.a., sulfuric-peroxide mixture or \u201cSPM\u201d) chemistry<\/a>.<\/p>\n<p>FSI has been pushing the envelope with wet cleans for many years, and <a href=\"http:\/\/www.solid-state.com\/articles\/article_display.html?id=247496\" target=\"_blank\">I\u2019ve talked with CTO Jeff Butterbaugh many times about this application<\/a>. Generally speaking, interconnect cleans have always allowed for more material losses than transistor cleans, and so had been considered as \u201cless critical.\u201d Being less critical, single-wafer process control was not considered as essential, so batch tools have dominated interconnect cleans. However, ever reducing process margins, material loss and galvanic corrosion in copper interconnects now suggest single-wafer control.<\/p>\n<p>\u201cThis order is important to us on many levels,\u201d said Don Mitchell, FSI\u2019s president and CEO. \u201cIt validates the critical capabilities of the ORION for 32nm applications. It also demonstrates this customer\u2019s conviction that those capabilities add sufficient value that even in a deep industry down-cycle, manufacturers are willing to invest in innovative technology, not only to prepare for the future, but also to realize current gains.\u201d<\/p>\n<p>The tool incorporates many of FSI\u2019s core technologies: in-line chemical blending and control, energetic aerosol chemical and water delivery, and recipe-driven procedures. Its modular design accommodates multiple chamber types and permits the addition of modules to increase maximum throughput. The ORION\u2019s unique closed-chamber design also permits the use of volatile, highly-reactive chemistries for single step, <a href=\"http:\/\/www.imec.be\/ScientificReport\/SR2007\/html\/1384081.html\" target=\"_blank\">all wet stripping of the highly implanted photoresist created during the fabrication of 32nm devices<\/a>. By eliminating ashing, it not only reduces material loss but also decreases the cycle time, process complexity and the number of tools and process steps.\u00a0 \u2013E.K.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>FSI International, Inc. (Nasdaq: FSII) announced December 23, 2008 that it has received an order for it\u2019s new ORION\u00ae single wafer cleaning platform after a beta evaluation by a major semiconductor manufacturer. The tool will be used for resist strip in 32nm metal interconnect modules, using FSI\u2019s proprietary \u201cViPR\u201d extension of the classic \u201cpiranha\u201d (a.k.a., [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[9,3,4,8],"tags":[30,32,17,31,12,28,29,34],"class_list":["post-15","post","type-post","status-publish","format-standard","hentry","category-equipment","category-manufacturing-fabrication-line","category-integrated-circuit","category-market-segment","tag-32nm","tag-beta","tag-clean","tag-interconnect","tag-semiconductor","tag-single-wafer","tag-spm","tag-vipr"],"_links":{"self":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/15","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=15"}],"version-history":[{"count":9,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/15\/revisions"}],"predecessor-version":[{"id":81,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/15\/revisions\/81"}],"wp:attachment":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=15"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=15"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=15"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}