{"id":844,"date":"2009-08-26T11:15:34","date_gmt":"2009-08-26T18:15:34","guid":{"rendered":"http:\/\/www.betasights.net\/wordpress\/?p=844"},"modified":"2014-09-13T09:27:32","modified_gmt":"2014-09-13T16:27:32","slug":"dualing-3dic-consortia","status":"publish","type":"post","link":"http:\/\/www.betasights.net\/wordpress\/?p=844","title":{"rendered":"Dualing 3DIC consortia"},"content":{"rendered":"

IMEC\/F-IZM\/SUSS\/TM vs. SEMATECH\/Leti\/EVG\/Brewer.<\/strong><\/span><\/p>\n

The leading R&D consortia have aligned (pun intended) with leading equipment and materials suppliers to create ultra-thin silicon wafer handling technologies for 3D ICs. With the ability to shrink circuit dimensions in 2D becoming ever more difficult, most of the world\u2019s IC fab leaders are evaluating the use of the 3rd dimension. In addition to the EMC3D suppliers\u2019 consortium, all of the leading IC technology R&D consortia (IMEC, Fraunhofer-IZM, Leti, and SEMATECH) now have 3DIC programs in place with equipment and materials suppliers.<\/p>\n

\"\"<\/a>IMEC<\/a> and SUSSMicroTec<\/a> recently started a joint development program. Together, they will develop permanent bonding, temporary bonding and debonding processes for 3D system integration, including through-silicon-via (TSV) manufacturing. IMEC will use SUSS \u2019s XBC300 production wafer bonder platform (see figure<\/em>) to develop 200 and 300mm permanent metallic interconnect bonding, as well as temporary bonding and debonding solutions for its 3D-stacked Interconnect and 3D Wafer Level Packaging technology. The bond cluster also includes a spin coater, a low force bonder and a plasma chamber. The XBC300 temporary bond configurations are available for development and high volume needs.<\/p>\n

For its 3D IC technology, IMEC uses a process flow where TSVs are realized in a single-damascene process that is performed immediately after active-device and contact processing but prior to formation of interconnect metallization layers. This process enables small via diameters of 1\u20135micron. After completion of the back-end wiring, silicon is removed from the bottom of the substrate to open the buried TSVs. Dice or wafers subsequently are stacked and interconnected in a wafer bonding step.<\/p>\n

\u201cWe are very pleased to co-develop with SUSS MicroTec the processes for permanent and temporary wafer bonding for our 3D technologies,\u201d said Eric Beyne, Program Director of IMEC\u2019s Advanced Packaging and Interconnect Research Centre. \u201cIn particular, the debonding and handling of very thin wafers ranging from 25 to 50 \u00b5m is an especially challenging and critical process. We are convinced that the versatility of the SUSS wafer bonding and debonding tool platform will contribute to bringing 3D integration technology to maturity.\u201d<\/p>\n

SUSS\u2019s XBC300 production wafer bonder is matched with material from Thin Materials (company in stealth mode) to create the temporary bonding solution to be used for challenging thin wafer handling. This material is capable of handling wafer processing temperatures in excess of 250\u00b0C, but can be de-bonded\u00a0 at room temperature. Fraunhofer-IZM works with the team at Thin Materials, too.<\/p>\n

\u201cThin Materials\u2019 technology for temporary bonding perfectly complements our process offering portfolio for 3D Integration and Packaging\u201d, confirms Frank Averdung, President and CEO of SUSS . \u201cPartnering with Thin Materials allows us to offer our customers a wide variety of temporary bonding technologies according to their specific needs.\u201d Together with its partners 3M, Disco, DuPont, NEXX Systems, Surface Technology Systems, and Thin Materials, the company hosted a TSV 3D Integration workshop introducing solutions for temporary bonding and thin wafer handling on July 15th during SEMICON West.<\/p>\n

Meanwhile, CEA-Leti continues to work with EVG and Brewer Science on temporary bonding for 3D ICs<\/a>. Thorsten Matthias, director of technology for EVG North America, presented \u201cThin Wafer Handling and Chip Stacking for 3D Integration\u201d at the SEMICON West Test, Assembly & Packaging TechXPOT<\/a>.<\/p>\n

\"\"<\/a>SEMATECH<\/a> has purchased an EV Group wafer bonder with \u201cSmartViewNT\u201d<\/a> technology (see figure<\/em>) for TSV wafer-to-wafer (W2W) bond alignment. The alignment uses a high-precision stage that comprises top- and bottom-side microscopes to ensure the highest degree of accuracy for all types of alignments, including face-to-face, backside and infrared-transparent. Initial results for W2W alignments demonstrated <0.3 \u00b5m face-to-face alignment accuracy, eliminating the need for post-processing steps such as generating backside alignment keys.<\/p>\n

\u201cWe\u2019re seeing a pivotal shift in the industry, where equipment suppliers and research institutions and universities alike are beginning to rally together and work in greater collaboration in preparation for when the market rebounds,\u201d said EVG vice president and general manager, North America, Steven Dwyer. The company claims an increase in orders for pilot line production service, indicative of widespread industry interest in 3D.<\/p>\n

EVG and Applied Materials are working together<\/a> as part of EMC3D<\/a> on wafer-bonding processes for stacking using TSV. As reported by BetaSights in April 2009, Applied Materials is working with Disco on wafer thinning<\/a>. Disco is working with SUSS. Nonetheless, SUSS\u00a0 and EVG are still strong competitors and are NOT working together.<\/p>\n

\"\"<\/a>Olympus Integrated Technologies America, Inc. (Olympus-ITA)<\/a> has provided an infrared (IR) inspection and defect review system (see figure<\/em>) with metrology software to SEMATECH for its 3D R&D Center at the College of Nanoscale Science and Engineering\u2019s (CNSE) Albany NanoTech Complex. The system\u2014installed and accepted in April, 2009\u2014enables SEMATECH to verify alignment of bonded wafers and TSV. \u201cWe have been collaborating with SEMATECH on inspection and defect review tools since 2001 and working with the 3D group since last year to provide a method to image and measure overlay offsets after wafers have been bonded together,\u201d said Olympus-ITA president Greg Baker.<\/p>\n

With so many alliances developing so many technologies, there were so many events during SEMICON West 2009 that it seemed impossible to attend them all. Fortunately, one of the more interesting events was recorded and archived. A panel discussion held both live (for an hour during SEMICON West) and in virtual space (for three weeks, shown as part of PR agency MCA\u2019s \u201cBrightSpots\u201d 3D IC Forum, with excellent text and multimedia links still available online<\/a>) brought together representatives from SEMATECH, Synopsys, Yole Developpement, EVG, and Terrazon Semiconductor. Paul Lindner, EVG’s executive technology director, offers his viewpoints on the role of wafer bonding and thin-wafer handling with Bob Patti, CTO of Tezzaron, chiming in from the manufacturing side (see YouTube video<\/em>).<\/p>\n

The BrightSpots 3DIC forum was moderated by Francoise van Trapp, formerly an editor with Advanced Packaging magazine, and now working with ex-SEZ technology executive Leo Archer on web-based 3Dincites.com<\/a> (rhymes with \u201c3D in-sights\u201d). There\u2019s no doubt that 3D is one of the most important technology concepts in ICs today, so it\u2019s great that veterans like Trapp and Archer are working to provide a continuous source of information about this vital direction. \u2013E.K.<\/em><\/p>\n","protected":false},"excerpt":{"rendered":"

IMEC\/F-IZM\/SUSS\/TM vs. SEMATECH\/Leti\/EVG\/Brewer. The leading R&D consortia have aligned (pun intended) with leading equipment and materials suppliers to create ultra-thin silicon wafer handling technologies for 3D ICs. With the ability to shrink circuit dimensions in 2D becoming ever more difficult, most of the world\u2019s IC fab leaders are evaluating the use of the 3rd dimension. […]<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[9,3,4,10,6,8,11],"tags":[78,466,307,31,468,224,272,76,310,135],"class_list":["post-844","post","type-post","status-publish","format-standard","hentry","category-equipment","category-manufacturing-fabrication-line","category-integrated-circuit","category-material","category-micro-electro-mechanical-system","category-market-segment","category-service","tag-3d","tag-integrated-circuit","tag-inspection","tag-interconnect","tag-micro-electro-mechanical-system","tag-metal","tag-process","tag-rd","tag-thinning","tag-tsv"],"_links":{"self":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/844","targetHints":{"allow":["GET"]}}],"collection":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=844"}],"version-history":[{"count":14,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/844\/revisions"}],"predecessor-version":[{"id":1311,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=\/wp\/v2\/posts\/844\/revisions\/1311"}],"wp:attachment":[{"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=844"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=844"},{"taxonomy":"post_tag","embeddable":true,"href":"http:\/\/www.betasights.net\/wordpress\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=844"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}