Monday, April 6th, 2009
Applied Materials and Disco announced a joint effort to develop wafer thinning processes for fabricating through-silicon vias (TSV) for future 3D IC stacks. The two companies, world leaders in thin-films and thinning (respectively) for silicon wafers, will be working together to develop integrated, high-performance process flows intended to lower the cost, reduce the risk and accelerate time to market for customers’ next generation chips.
Applied Materials CMP, deposition, and etch tools used in TSV integration (source: Business Wire)
Combining Disco’s precision grinding equipment with Applied’s etch, dielectric deposition, physical vapor deposition and chemical mechanical planarization systems (see figure), the two companies expect to develop wafer thinning and post-thinning processes of wafers bonded to silicon and glass “handle” wafers. Nobukazu Dejima, president of Disco Hi-Tec America, said, “The capability to validate complete process flows using thinned wafers at our Santa Clara research laboratory and Applied’s Maydan Technology Center gives us a unique opportunity to exploit the advantages of thinned wafers in multiple TSV integration schemes.”
Not all chips today have to be ultra-thin, and the joint effort will work on a variety of targets for the final silicon thickness. “The final silicon thickness in the context of the announcement will be 30 to 200 microns, depending on the customer,” said Sesh Ramaswami, senior director of strategy for the silicon systems group at Applied Materials, to BetaSights. In addition to the possible use of plasma etch to remove post-grind backside damage, plasma etch in combination with thin-film deposition steps may also be used to develop integrated processes to engineer the backside structure of the exposed TSV. “The customer can’t really afford to do it,” explained Disco spokesman Scott Sullivan. Working together, Applied and Disco will share information, and hope to give customers a drop-in solution to the most demanded TSV process flows.
We’ll see 3D directions at the IEEE International 3D Systems Integration Conference (I3DSIC) that will occur in San Francisco for the first time, September 28-30. Abstracts are due May 15, with final papers by July 1st for this conference that combines the previous ASET/IEEE-EDS sponsored I3DSIC held in Tokyo in 2007 & 2008 and the IEEE-CPMT sponsored I3DSIC held in 2005 & 2007 in Munich. More on TSV technology and exclusive comments by Sullivan and Ramaswami will be in the next BetaSights Newsletter. –E.K.