Posts Tagged ‘3D’

Thursday, September 23rd, 2010

TSV for 3D integration of heterogeneous ICs used in interposers first, as shown at SEMICON/West, IMAPS, IEDM and companies like ASE, Alchimer, Suss, EVG, Novellus, Vertical Circuits, and IBM.

Friday, January 22nd, 2010

The IEEE’s International Electron Devices Meeting (IEDM) is still the place to see the latest micro- and nano-electronics research targeting commercial markets. On December 8, 2009, French researchers from Leti/Minatec showed “3D sequential CMOS integration” as <600°C processing of PFETs using a (110) orientation FDSOI layer that was transferred on top of NFETs made using […]

Wednesday, August 26th, 2009

IMEC/F-IZM/SUSS/TM vs. SEMATECH/Leti/EVG/Brewer. The leading R&D consortia have aligned (pun intended) with leading equipment and materials suppliers to create ultra-thin silicon wafer handling technologies for 3D ICs. With the ability to shrink circuit dimensions in 2D becoming ever more difficult, most of the world’s IC fab leaders are evaluating the use of the 3rd dimension. […]

Friday, May 1st, 2009

Leaving California for the first time, the 12th annual IEEE International Interconnect Technology Conference (IITC) will take place in Sapporo, Japan, June 1-3. With lithographic shrinks in 2D dimensions slowing, interconnects between chips in packages and in 3D stacks will be the driver for increased density and functionality in ICs. Thus, the more than 80 […]

Monday, April 20th, 2009

The Materials Research Society (MRS) Spring Meeting in San Francisco is so huge, this year attracting a record of over 5,000 attendees, that strategy is needed to try to see any representative sample of the event. To provide in-depth information about new materials technologies, new symposia have been added over the years such that there […]

Monday, April 6th, 2009

Applied Materials and Disco announced a joint effort to develop wafer thinning processes for fabricating through-silicon vias (TSV) for future 3D IC stacks. The two companies, world leaders in thin-films and thinning (respectively) for silicon wafers, will be working together to develop integrated, high-performance process flows intended to lower the cost, reduce the risk and […]

Wednesday, April 1st, 2009

Asahi Glass is promoting a family of new photosensitive spin-on-dielectric (SOD) films for fan-out WLP and 3D packages, as well as for FPD and MEMS applications. The Chemicals Fluoroproducts Division of Asahi Glass has successfully developed the AL-X polymer series, primarily targeting the redistribution/rewiring layers in fan-out WLP packages. The company will begin production of […]

Monday, March 16th, 2009

The BetaBlog of March 5th was originally titled “Amkor chooses TMV not TSV for PoP” and Amkor’s stalwart vice president of business development Lee Smith contacted BetaSights to correct the impression that Amkor may have chosen to not work on TSV. I’d intended the original title to be somewhat playful; since TSV is chip-level while […]

Thursday, March 5th, 2009

Amkor Technology announced today that it will introduce its next generation package on package (PoP) platform at the IMAPS Device Packaging Conference next week in Scottsdale, AZ. Again begging the question, “Who needs TSV?” this this new PoP platform uses Amkor’s proprietary through mold via (TMV)(TM) interconnect technology to get to 3D IC stacking. {Blog […]

Tuesday, March 3rd, 2009

IEDM 2008 included the unveiling of Schiltron’s (Session 34.6) revolutionary 3-D high density Flash technology that combines the smallest TFTs to date in series strings of up to 64 cells. The unique architecture effectively removes pass disturbs allowing large worst-case string currents and resulting in thinner tunnel oxides, lower erase voltages, and higher endurance than […]