Posts Tagged ‘interconnect’

Wednesday, June 16th, 2010

Intel shows vertical integration pays off with air-gaps through manufacturing cost reduction in low-k dielectrics for 32nm and 22nm node IC interconnects.

Wednesday, August 26th, 2009

IMEC/F-IZM/SUSS/TM vs. SEMATECH/Leti/EVG/Brewer. The leading R&D consortia have aligned (pun intended) with leading equipment and materials suppliers to create ultra-thin silicon wafer handling technologies for 3D ICs. With the ability to shrink circuit dimensions in 2D becoming ever more difficult, most of the world’s IC fab leaders are evaluating the use of the 3rd dimension. […]

Friday, August 21st, 2009

James Quinn, CEO of Replisaurus, has been very busy executing for the last few years to bring his vision of a new metallization technology to the IC fab industry. Targeting the formation of Cu interconnects for advanced packaging applications, Quinn has assembled a great team to work with CEA-Leti and other industrial partners on a […]

Tuesday, March 17th, 2009

Breaking news about a leading porous low-k (PLK) material from Japan was first revealed in the SemiNeedle Planarization Lounge Forums ( about two months ago. During an expert panel discussion on CMP integration with low-k materials (moderated by this editor, summarized in “Chemical-Mechanical Planarization (CMP) technology consensus 09Q1” publication available at the site), Dick James, […]

Wednesday, February 4th, 2009

Allvia, the first through-silicon via (TSV) foundry, has secured $5 million from private investors in a round of funding to expand manufacturing facilities and to build more capacity. After 3 years of revenue generation from providing vertical interconnects and System-in-Package (SiP) solutions, total investment in the company is now $25 million. With in-house processing equipment, […]

Wednesday, January 14th, 2009

Smart Equipment Technology (S.E.T.), a wholly-owned subsidiary of Replisaurus Technologies and a leading supplier of high accuracy die-to-die (D2D), die-to-wafer (D2W) bonding and nanoimprint lithography solutions, announced yesterday that it will collaborate with IMEC on 3DIC R&D. IMEC’s 3D integration program explores 3D technology and design for applications in various domains, focusing on 3D WLP […]

Monday, January 5th, 2009

FSI International, Inc. (Nasdaq: FSII) announced December 23, 2008 that it has received an order for it’s new ORION® single wafer cleaning platform after a beta evaluation by a major semiconductor manufacturer. The tool will be used for resist strip in 32nm metal interconnect modules, using FSI’s proprietary “ViPR” extension of the classic “piranha” (a.k.a., […]