Monday, July 25th, 2011

Today, Innovalight’s founders and investors are celebrating the company’s official acquisition by chemical giant DuPont. Terms of the deal were not disclosed, but Innovalight should have been able to negotiate from a position of strength due it’s selective-emitter (SE) ink technology being taken up by JA Solar, Jinko, Motech, and Yingli among other crystalline-silicon (c-Si) photovoltaic (PV) manufacturers.

Doped-silicon inks from DuPont Innovalight enable the production of selective emitter solar cells with the addition of a single screen printing step.

Doped-silicon inks from DuPont Innovalight enable the production of selective emitter solar cells with the addition of a single screen printing step.

Innovalight based in Sunnyvale, California has developed a functioning “solar ink”-composed of phosporous-doped silicon nanoparticles-that can be screen printed to form SE regions in a single additional step as part of a c-Si PV fab line. DuPont, based in Wilmington, Delaware, earned more than $1 billion in sales revenue in the photovoltaic market in 2010, much of it revenue from the company’s “Solamet” line of silver metallization pastes.

Since the advantage of SE in PV cells is found in integration with the top-side metalization, DuPont’s PV metallization paste expertise should allow the company to optimize integration with SE inks. According to industry estimates, SE technology could represent 13 percent of crystalline silicon solar cell production by 2013 and up to 38 percent by 2020.

“Innovalight brings in-depth knowledge of solar devices, silicon technology and Selective Emitter technology, and DuPont adds expertise in materials science, manufacturing capabilities and global market access,” said Conrad Burke, founder – Innovalight. DuPont experience in production scale-up and manufacturing operations will accelerate time-to-market for Innovalight products and broaden customers’ access to the technology.

JA Solar vouches for Innovalight

At the Spring 2011 Materials Research Society meeting in San Francisco (C4.2), Yong Liu of JA Solar presented an invited paper on “Comparative Study on Manufacturability of Selective Emitter and Double Printing,” based on the Innovalight ink for SE.

The phosphorous-doped ink is screen printed prior to blanket phosphorous deposition, such that n++ silicon is formed where contacts will be later printed while n+ remains across the rest of the wafer surface:

  1. Surface Texture etch,
  2. Ink print and bake [the only new step],
  3. POCl Diffusion (tube furnace),
  4. Plasma edge isolation/glass-removal,
  5. PECVD SiNx ARC/passivation.
  6. Metallization printing back and front,
  7. Furnace firing, and
  8. Testing binning.

The SE process is robust and cost-effective. “We’ve demonstrated 1.2% absolute efficiency gain in our R&D lab,” said Liu. “In manufacturing we can get around 1% absolute efficiency gain, with cells off of the line showing about 18.5 percent median efficiency ignoring low outliers due to poor wafer quality.” The selective emitter structure reduces surface recombination losses, and so improves the spectral response at short wavelengths. SE reduces contact resistance from ~80 Ohms/sq to 65 Ohms/sq, compared to ~70 Ohms/sq as the practical limit for mass production using POCl alone.

The double-printed front contact allows for the fingers to have much higher aspect-ratio and improved conductivity. The maximum height in a single screen print is generally 18-20 microns, while double-printing can get to ~30 microns height for ~30 microns width, corresponding to an increase in the fill-factor from ~78% to ~80%. The printing process happens every 3 seconds, and the screen must be very rigid so stainless steel actually deforms too much in HVM, and improvements are needed to be able to do double-printing.

JA Solar ran 100k wafers (3 days production) comparing SE and DP, and the cell-level efficiencies were 18.6 and 18.2 percent (respectively). Double-printing seems to be redundant when SE is already in use. “The reason is that the SE underneath sheet resistance is very low, so you don’t need double-printing and it’s kind of redundant,” explained Liu. —E.K.

Wednesday, June 15th, 2011

Ultra-pure water vapor for solar cell processing improves PV efficiency by eliminating the impurities that would otherwise trap charge carriers. However, conventionally ways to get ultra-pure water vapor in high-volumes tend to be expensive and unreliable. Ultra-pure steam can easily be made by flowing oxygen and hydrogen gases though a catalytic chamber, and while this has been used for some IC fab processes it is too expensive to be used in PV lines.

RASIRC Steamer (source: RASIRC)

RASIRC Steamer (source: RASIRC)

PV fabs have “mostly-pure” de-ionized water (DI) available, however, so how hard is it to make ultra-pure steam? In the real world it is very hard to make steam with simple boilers and bubblers and evaporators for very long without something breaking down and contamination getting in. Residues build up in some places, and materials leach out of others. The insidious aspect of these cheap and dirty solutions is that everything seems fine for the first few weeks or months, until slight yield and efficiency losses slowly begin.

Rasirc has been selling and supporting high-flow ultra-pure steam generators in the IC industry for many years, and has proven its systems screen all volatiles, ionics, and other impurities from steam generated from DI water. Applied in critical solar cell manufacturing processes, the parts-per-trillion (ppt) pure steam can actually increase yields. The foundation of the system is a non-porous membrane which allows steam through at a flow rate of up to 50 slm, while excluding metals, hydrocarbons, and particles. All internally wetted surfaces and seals are either quartz or teflon to be safe.

The Fraunhofer Institute for Solar Energy Systems (ISE) recently announced that using the Rasirc steamer in the production of back contact silicon solar cells the efficiency reached 20.2%. Fraunhofer used the steamer to provide ultra-pure water vapor for its metal wrap through (MWT) and passivated emitter and rear cell (PERC) solar cell flows.

“It has been a very productive and positive experience working with the engineers from Fraunhofer ISE,” said Jeffrey Spiegelman, president of Rasirc. “It is very exciting to be an important part in bringing MWT/PERC cells to mass production.”

The membrane purifier technology has been used in production lines of IC fabs for processes including “wet oxidation” and atomic-layer deposition (ALD). In both cases, the process may involve deposition or growth of a layer within the active transistor structure itself, and so metallic and other impurities cannot be tolerated. Rasirc reported last year that improved device results led to multiple steamers being sold to multiple crystalline silicon PV lines in China.

Thermal silicon oxides are known to effectively passivate silicon surfaces and have been used for the fabrication of highly efficient silicon solar cells. The previous standard solution for steam in wet oxidation furnaces is combustion of hydrogen and oxygen gases in a “torch”, but this technology comes with safety and maintenance issues, and growth-rate varying when the gas flows drift over time.

This membrane-based steam delivery system does not just prevent contamination from getting through, it also ensures that the vapor arriving at the process chamber is pure steam. By delivering consistent ultra-pure H2O with no H2 nor O2, the RASIRC steamer allows for reliable growth of the oxidation layer at the maximum rate. The company claims that customers see 7-18% relative growth rate increases over the best possible using torches or bubblers. —E.K.

Tuesday, April 5th, 2011

The Japanese Society of Applied Physics announced that lithography pioneer Prof. Masato Shibuya of the Tokyo Institute of Polytechnics would receive the 2011 ‘Outstanding Optical and Quantum Electronics Achievement Award’ for his invention of the Phase Shifting mask and other contributions to semiconductor manufacturing. This JSAP Outstanding Achievement Award is also called the Takuma Award to honor the late Hiroshi Takuma, one of the leaders of the laser community in Japan. The presentation to Shibuya was scheduled to be made at the 2011 International Conference of the JSAP that was to be held at the Kanagawa Institute of Technology during March 24-27 of this year, but was postponed because of the recent catastrophes.

Dr. Masato Shibuya won the Takuma Award 2011

Dr. Masato Shibuya won the Takuma Award 2011

Dr. Shibuya is little known in the United States, but well recognized in Japan as the originator of many of the technologies that have so advanced optical lithography. As he recounts it, he had not studied optics deeply at university but found himself in an optical design department at Nikon in 1977. While working on early automatic lens design software (which became popular internally), he realized that the textbook formulations were not adequate for Nikon’s purposes and decided to re-derive partially coherent imaging from scratch.

Working out specific examples led to the realization that something had been left out in the standard analysis, and that controlling the phase shifts between features at the mask (or the angles of off axis illumination) in a stepper could improve resolution, depth of focus (DoF), etc. That realization led to the famous Shibuya Patent, filed in September 1980 and published (in Japanese) in April 1982. “Honestly speaking, if I were more knowledgeable, I would not have been able to get the idea,” Shibuya wrote in a memoir published in Japan.

The same idea had occurred to this author while at IBM in 1982, doing work to be published but not to obtain a patent. In 1984, Shibuya visited Fairchild Semiconductor in South San Jose, where he learned about this work at IBM (roughly one mile away) but maintained his low profile. The idea of phase-shift at the mask was later extended by Hasegawa of Hitachi and Lin of IBM into the attenuating or half-tone phase-shifting mask, which required new semi-transparent materials.

By breaking out of the “what you see is what you get” layout paradigm, Shibuya’s idea enables today’s essential resolution enhancement technologies, including optical proximity correction (OPC), sub resolution assist features (SRAFs) and source-mask optimization (SMO). Shibuya took a different route, helping Nikon to develop its laser illumination systems. After Nikon he became a professor at the Tokyo Institute of Polytechnics, published the two textbooks “Optical Diffraction and Imaging” and “Introduction to Lens Optics,” and continued to work on optical and lithography innovations. –M.D.L.

Monday, March 21st, 2011

The 2011 SPIE Advanced Lithography Symposium was noticeably different from previous meeting which highlighted new tools and methods. This year few hardware or software tools were innovative enough to be news worthy, rather it was all about materials and the remarkable things they could be made to do – or not do.

The two inventors of the alternating phase-shift mask (alt-PSM) review a poster during SPIE AL 2011. Prof. Masato Shibuya (left) now of the Tokyo Institute of Polytechnics in Atsugi and formerly of Nikon shows his poster presentation to Dr. M. David Levenson (right) now of BetaSights and formerly of IBM (source: SPIE)

The two inventors of the alternating phase-shift mask (alt-PSM) review a poster during SPIE AL 2011. Prof. Masato Shibuya (left) now of the Tokyo Institute of Polytechnics in Atsugi and formerly of Nikon shows his poster presentation to Dr. M. David Levenson (right) now of BetaSights and formerly of IBM. (source: SPIE)

Chip production has reached the practical limit of a single exposure of 193nm wavelength ArF immersion lithography. Going beyond with 193i exposure requires double-patterning (DP) and materials innovation, whether for the sidewall depositions in self-aligned double patterning (SADP), or for the convenient fixing of the initial photoresist pattern in multiple resist exposure methods (litho-etch-litho-etch “LELE”), or for something even more remarkable like directed self-assembly (DSA).

There was a separate conference devoted to the long hoped-for Extreme-Ultra-Violet Lithography (EUVL) production technology which would use 13.5nm exposure wavelength, but it has become clear that – for all the progress that EUVL has made and continues to make – it may not be ready for insertion before the 10nm node.

So, if the industry is going to make 10nm CD chips, it will have to be done with 193nm light – a wavelength 19X larger than the minimal feature size. The fact that the industry is contemplating such extreme sub-resolution lithography – at all – shows remarkable confidence in innovative materials and processes. Then, when the first EUV lithography tools arrive in the fab, they will be used with Resolution-Enhanced Technology (RET) since the nominal feature size will still be smaller than the exposure wavelength!

Plenary Highlights

Luc Van den hove, President and CEO of IMEC, recognized this new reality and the societal imperative for continued innovation in the first plenary presentation. We have become people of bits and bytes, according to Van den hove, communicating with everyone and everything using semiconductors in an amazing world – when it all works. Keeping it working requires continued scaling beyond the limits of ordinary silicon, planar chip designs, and DUV exposure. Van den hove foresaw the use of germanium and III-V materials in ~10nm chips and then a switch to tunnel junction transistors and 3D. Optical interconnects would speed I/O removing one present performance limit.

Of course the infrastructure to manufacture these amazing new chips has to be researched and developed now. Van den hove announced that IMEC had received the 20 truckloads from Veldhofen that would be reassembled into its NXE 3100 EUV scanner. That tool had passed qualification tests at ASML, printing 24nm line/space arrays and 26nm contact holes using dipole EUV illumination. For 15nm node production, Van den hove foresaw the use of similar EUV tools in a double patterning regime!

In his plenary talk, Shang-Yi Chiang, senior vice president of R&D at TSMC warned about the cost of all of this innovative production. He expressed the belief that ArF immersion lithography would prove too expensive beyond the 20nm node, but that there was hope that EUVL, multi-beam EbDR or some combination would prove economically viable. However, cost reductions elsewhere – perhaps through automation and a move to 450nm wafers around 2016 – would also be needed to make the new technologies competitive with the old.

Advances in Resist & Processing

Three keynotes highlighted the challenges and opportunities for the materials that register patterns on wafers in this new era. Patrick Naulleau, Interim Director of the Center for X-ray Optics at Lawrence Berkeley Laboratories (LBL), reviewed the progress (or lack thereof) in EUV resists. A viable resist must combine sufficient resolution, high sensitivity, and low Line Edge Roughness (LER) – and so far, none have done so, according to Naulleau. Progress with conventional Chemically-Amplified Resist (CAR) has stalled, possibly for fundamental reasons, whereas a non-CAR resist has shown 15nm resolution at 70mJ/cm2 sensitivity.

LER is a knotty problem, said Naulleau, with some of it coming from the mask, some from the resist-wafer interface, and some from resist exposure and development statistics. A LBL experiment found 3.4nm of correlated LER on multiple exposures of the same slightly out-of focus mask location. That result was attributed to the ~1nm reticle substrate roughness behaving like a noisy pure phase mask instead of a plane reflector. To get to 1nm LER, Naulleau predicted that 80mJ/cm2 sensitivity would have to be tolerated, and the aerial image contrast raised above 80% with perfectly flat mask substrates.

Bill Hinsberg, late of the IBM Almaden Research Center, described the lab-to-fab transition underway for DSA. In this process, phase-separation converts special block co-polymer films into technologically useful patterns as directed by topographic or chemical features imprinted on the substrate. The self-assembled structures can have a finer pitch than any conventional lithographic technique. The trick is to get the desired shapes without defects, and properly registered to whatever has been pre-patterned below. Hinsberg cited some examples from the conference and pointed out that there were broad opportunities for future materials and process development.

James Thackeray of Dow Electronic Materials then reviewed the continuing progress in materials targeted for sub-20nm lithography, which likely will be in pilot production at some NAND fab before the next conference. The Line Width Roughness (LWR) of CAR can be reduced by attaching the photo-acid generator (PAG) moiety to the polymer so as to prevent aggregation, he reported. This technique also reduces resist outgasing during exposure, preventing EUV optics contamination. CAR resist chemistry is extremely adaptable, and can meet the challenge of EUV and sub-20nm device production, averred Thackeray. He did not say it would be easy or profitable.

Negative Tone Development

Several sessions explored one remarkable example of CAR resist adaptability, negative tone development. The earliest industry photoresists were negative tone materials in which light exposure caused polymers to crosslink and become insoluble, but were entirely replaced by positive tone resists where exposure increased the rate of dissolution in an aqueous base. The problem when pushing resolution limits with negative tone resist is that the crosslinked polymers are insoluble, but absorb solvent and swell in all directions, as describe by Christopher Ober of Cornell University. This prevents good CD control and converts straight resist lines into wavy serpentines, unusable in electronics.

A more fundamental limit for positive resists, however, is that the dimensions of dissolved-away features (such vias and trenches) are limited by the wavelength of light. Negative resist would be desirable to print such features since the dimensions of dark features can be arbitrarily small, in principle (i.e. there is no wavelength of darkness).

When conventional CAR resists are developed in non-polar organic solvents instead of aqueous base, they become negative tone. The reason, according to Ober, is that the acid-catalyzed de-protection of carboxyl groups on the resin makes that material highly polar and insoluble in non-polar solvents. In aqueous base developers, those carboxyl groups enhance the solubility, exactly the opposite effect, with the result that only the unexposed hydrophobic material remains on the wafer. So, it turns out that solvent development can make yesterday’s positive CAR resist negative, a fact that has apparently been forgotten since Apex-E replaced t-BOC in the early 1980’s. In addition, the LER is reduced because of the greater optical and solubility contrast.

Several subsequent speakers elaborated on the use of negative tone developers (NTDs) which are typically non-polar organic solvents like n-heptanone or anisol-ketone mixtures. All these developers cause some thickness loss in the exposed regions and all require special handling for safety and health reasons. According to Charles Pieczulewski of Sokudo, that is now being done in production with separate stand-alone development stations for the layers requiring NTD. Young Bae of Dow reported trenches down to 40nm HP (using a topcoat-free resist) with 193i exposure at 1.35NA and aggressive dipole illumination. Shinji Tarutani of Fujifilm reported contact hole patterns down to 38nm half-pitch (with crossed-grating double exposure) and a defect density of 0.06/cm2.

A considerable number of fundamental and practical issues remain unresolved and may prove to depend on the specifics of the polymer and developer employed. For example, Stewart Robertson of KLA-Tencor reported that current resist models absolutely forbid the large experimentally measured NTD exposure latitudes. Still, whatever the models say, it is clear that for trench and contact resist, darkness and negativity are back!

Spacer Double Patterning

Low temperature atomic layer deposition (ALD) SiO2 facilitates SADP with a variety of core materials, including photoresist, according to Hidetami Yaegashi of TEL. Such flexibility reduces the number of steps and costs in pitch splitting, according to Yaegashi. For example, a self-aligned quadruple patterning (SAQP) to 11nm HP takes only 7 steps! Yaegashi predicted self aligned double patterning (SADP) would be cheaper than EUVL at 22nm unless the EUVL stepper throughput was >100wph. SADP processes can also produce the registration layers need for further pitch splitting by DSA. Koutaro Sho of Toshiba seconded the idea of depositing SiO2 over resist cores, but advocated a separate slimming process instead of over-exposure or over-development.

Other multiple deposition and selective etch processes lead to ever finer and more exotic structures. For example, TEL and Dennis Hsu of Nanya Technology revealed similar processes to fabricate <30nm contact arrays that begin with a square array of pillars that are sidewall coated just enough to leave empty space in the centers of the squares. Etching away the pillars and through the spaces transferred a ~40nm pitch split contact pattern to the wafer.

Recessive Self-Aligned Double Patterning (RSADP) process flow shown in cross-sectional schematics (source: Applied Materials)

Recessive Self-Aligned Double Patterning (RSADP) process flow shown in cross-sectional schematics. (source: Applied Materials)

Other multiple patterning options (figure) were presented by Christopher Bencher and colleagues from Applied Materials in oral and poster papers at both the resist and optical lithography meetings. The key point made by Bencher was that the role of lithography has changed to generating a mandrel (a core or pre-pattern) around which patterns will be fabricated with various degrees of density multiplication. Thus it is no longer the exposure process that matters; it is the subsequent deposition and etches.

Recessive Self-Aligned Double Patterning (RSADP) results for contact holes density doubling to 50nm half pitch. (source: Applied Materials)

Recessive Self-Aligned Double Patterning (RSADP) results for contact holes density doubling to 50nm half pitch. (source: Applied Materials)

Applied Materials supports various mandrel, sidewall, hard-mask, and sacrificial layer material depositions that can be etched with various degrees of selectivity or isotropy to fabricate the desired result. Self-aligned double-, triple-, and quadruple-patterning can fabricate complex poly and metal layer structures for 15nm node logic. Yijian Chen, and a team from the Mayden Center highlighted the use of the different etch properties of a-Si, poly-Si, a-C, oxide, and nitride for such processes. Among the more daring variants is the recessive SADP (RSADP) process, which can be elaborated using additional materials for triple and quadruple splitting. Etch steps 2-4 and 6-7 can be combined into single recipes, and the flow can create contact holes (figure). Obviously, more development is required of this new paradigm.

Directed Self Assembly (DSA)

Complex organic materials have been assembling themselves into potentially useful structures since before life began, but controlling that proclivity in semiconductor manufacturing requires a leap of imagination. Not only must the chemically driven patterns be registered properly for subsequent processing, but the defect level and CDU have to meet industry specifications over full 300mm wafers.

Those requirements have now been fulfilled, according to Chris Bencher and a team from Applied Materials and IBM Almaden Research Center. Their process on full 300mm wafers chemically pinned the PMMA of a PMMA-polystyrene block co-polymer to a lift-off patterned Si-BARC layer to produce ~12nm line/space arrays with 3:1 pitch division. Etching the polystyrene away left 25nm-pitch PMMA lines, 25nm tall, which could then act as a resist layer for pattern transfer into hardmask layers. An optimized process showed no dislocations in the grating pattern and other DSA failure modes were located at the “streets” between lithographic exposure fields where the direction for self-assembly is less clear. The total defectivity was 25/cm2 according to a UVision inspection at 12nm sensitivity – and most defects were particles.

Since DSA requires only some “new bottles of goop,” according to Gregg Wallraff of IBM, it may prove the most economical pitch splitting method. Numerous papers elaborated on the potential for combining 193i with DSA of lamellae to fabricate fine spaced gratings for line-and-cut circuit designs. Others described the fabrication of imprint masters for patterned-media hard disc drives using DSA. The most desired patterns for disc drives are tracks with rectangular domains with a 2:1 aspect ratio, and Elizabeth Dobisz of Hitachi Global Storage explained how such masters could be built with 27nm down-track pitch and 27nm track width. E-beam lithography can directly write the anchoring layer of the lamellar pattern and also cut the lamellae to define tracks at a density of 500Gb/ Six times that density could be obtained if the read/write heads could adapt to hexagonal arrays of round domains.

EUV Lithography

The ASML NXE:3100 EUVL stepper. (source: ASML)

The ASML NXE:3100 EUVL stepper. (source: ASML)

The massive EUV lithography ecosystem slogs on in spite of the skepticism, expressed by Sam Sivakumar of Intel and others, that it may not be ready in time for 10nm node design rule (DR) validation nor for volume production in 2015. Christian Wagner of ASML described the performance of their pilot production tool, the NXE:3100 (figure), two of which have been shipped to customers.

Six lenses have been built with flare <5% reported Wagner. Wafer throughput today is 5wph with 10W sources and, and will rise 10-fold when 105W sources are installed in the first NXE:3300 production tool at the end of the year. Lines and spaces (L/S) have been imaged below 27 nm with 2 nm CDU, and contact hole arrays formed at 60nm pitch and diameters down to 26 nm with conventional illumination. At 32 and 40 nm diameters, the Mask-Error Enhancement Factor (MEEF) is 2 with a 1.8 nm CDU. Using dipole illumination allows for printing of 22 nm L/S arrays with 1.9 nm CDU, 500 nm DOF, and 10% EL.

The machine has been exercised with real 18 nm SRAM metal and contact hole patterns yielding CDU <3nm. Dedicated chuck overlay is <4nm to allow for DP, and stage accuracy is <2nm. Reticles can be handled for 40 cycles before an additional particle is detected, and <3 particles of 40nm-size are dropped on a wafer during a pass. Wager said that Brion Technologies is working on the remaining imaging issues including flare, shadowing, and scattered radiation at chip edges due to reflection by the blades that define the illuminated field at the wafer.

The NXE:3300B EUV stepper for production will be available in late 2012, with a 0.33NA and a flexible EUV illuminator to facilitate improved resolution through source-mask optimization (SMO). With 15mJ/cm2 resist sensitivity and a 250W source, the throughput would be 125wph, according to Wagner.

The first paper about the first NXE:3100 in a fab was by Sungmin Huh of Samsung. He used the EUV scanner to validate different inspection strategies using wafer exposures. The issues all seemed to relate to mask defects, 75% of which came from the substrate and which could not always be detected until they printed on the wafer. Of the 5 mask blank inspection tools tested, only 2 worked at 32nm and one at 16nm. Surprisingly, even wafer inspection did not reveal all the wafer defects! He recommended patterning the EUV absorber in a way that known blank defects are hidden.

Thus in spite of all the progress made on exposure tools, potential insertion of EUVL continues to lag due to delays in ancillary apparatus development, such a mask inspection tools and illumination sources.

EUVL Sources

Two distinct types of EUV sources are being developed by 3 vendors, electrical-Discharge Produced Plasma (DPP) by Xtreme Technologies (now 100% owned by Ushio) and Laser Produced Plasma (LPP) by Cymer and Gigaphoton (50% owned by Ushio). Wagner reports that ASML has integrated four LPP sources that give 80W power at 50% duty factor, and the first DPP source producing 61W at 20% duty factor has also been integrated.

As described by Marc Corthout the Xtreme DPP source uses molten tin transported by two rotating wheels towards the gap between them. A small laser ablates and ionizes a little tin at the gap, which completes a circuit, discharging a 5J capacitor and producing an EUV emitting plasma. Running at up to 40,000 pulses-per-second (pps), the Xtreme system produces 15W of clean EUV at the intermediate focus with +-0.2% dose stability, 0.04% repeatability, 80% uptime, and 1 year lifetime for the collector shells and foil trap. An argon buffer and sputtering keep the condenser optics clean. The first source has been shipped to IMEC. Corthout predicts that higher rep rate energy per pulse will produce 100W by year end, and that the new system designed for the NXE:3300 will produce 350W total. Without the complexity of a drive laser, the DPP system seems quite small.

The Cymer LPP system now produces 11W of clean EUV power at the intermediate focus (IF), averaged over the duty cycle, according to David Brandt of Cymer. It will employ a small laser pre-pulse to prepare a tin droplet for EUV emission with 3% conversion efficiency driven by a much larger laser pulse. He also claimed to meet the 0.2% dose stability spec. and plans to double output by June, all with internal R&D funding. Cymer has produced 10 collector mirrors and has learned how to keep them clean using hydrogen buffer gas. The ASML NXE:3300B tool needs a different and smaller source design, with a 40kW laser and 100kHz drive to produce 250W of EUV at an electricity cost of $350,000/year.

The third EUV source company, Gigaphoton, is targeting October 2011 to demonstrate the GL200E as a 250W source for the NXE:3300B stepper, and is not attempting to support earlier designs. This LPP system uses a short wavelength pre-pulse to vaporize the 20 micron diameter tin droplet before 10.6 micron wavelength driver laser irradiation, achieving 3.3% conversion efficiency with no debris. The force field of a superconducting magnet shields the collector mirror from charged particles, while hydrogen buffer gas controls the rest. In a private interview with BetaSights, Haruku Mizoguchi of Gigaphoton, described a 7 hour experiment in which a 3.6kW CO2 laser pulsing at 100 kHz produced 20W of clean EUV at a 5% duty cycle. Upgrading the laser to 23kW and the conversion efficiency to 5% will produce 250W after spectral filtering, according to Mizoguchi. While the source chamber and magnet are relatively small, the laser system in the sub-fab is absolutely gigantic!


The likelihood that the first production EUV tools will have to operate with k1 factors below 0.5 motivated several papers at SPIE Advanced Lithography. Off-axis and even flexible illumination is now plan-of-record at ASML, and their Brion Technologies division is investigating means of applying EUV proximity correction and even SMO. Perhaps the most remarkable RET paper (7969-119) was by Pei-Yang Yan and a team from Intel and LBL whose poster on fabrication and testing of an EUV alternating Phase-Shift Mask (alt-PSM) was presented orally on Tuesday morning (figure).

EUV alternating Phase-Shift Mask (alt-PSM) work by Intel and LBL, a) mask cross-section, b) absorber and phase-edge resist images, and c) 22nm line-space patterns. (source: Intel)

EUV alternating Phase-Shift Mask (alt-PSM) work by Intel and LBL, a) mask cross-section, b) absorber and phase-edge resist images, and c) 22nm line-space patterns. (source: Intel)

To achieve a 180° phase shift on a reflective 13.5nm mask at 6° off normal requires a phase step of only 3.39nm. Since that is too small to control, the Intel mask shop fabricated a range of substrate step heights hoping to bracket 420° phase shift at 10.18nm. After multi-layer coating, the phase edges were broadened, but were narrow enough to be largely covered by absorber material. Registering the absorber pattern to the phase steps required depositing a tall frame on the substrate that could be used for subsequent alignment in the second mask pattern generation step, reported Yan.

By shot-gunning offsets, the researchers found properly aligned regions where the images of the absorber and phase steps coincided at the correct effective phase-shift. Resolution was 5 nm better than a binary mask with on axis illumination, the line-end roughness (LER) was superior with particular benefit out of focus, and the alt-PSM dose to size was 30% lower than a binary mask with dipole illumination at the same resolution! The Intel-LBL work did not confront the shadowing predicted for EUV masks by an alt-PSM poster from TSMC, but it did illustrate the heroic measures needed to control the phase in EUVL (to ~0.1nm) given known substrate anomalies.

Optical Lithography Innovations

“Flexibility” was the key word for optical lithography this year, with both Nikon and ASML announcing flexible wavefront tuning and illumination. The second generation ASML FlexRay illuminator has been extensively qualified at IBM, according to Gregory McIntire and a team from the IBM consortium and ASML. The new mirror arrays have overcome the pixel wear-out syndrome plaguing the first generation and mirror assignment algorithms are being developed both to match OPC signatures among tools and to facilitate SMO. Kazuya Fukuhara of Toshiba showed how flexible illumination can avoid mask re-spins when the delivered reticles show defect hot-spots with standard c-quad illumination.

Nikon was much cagier about announcing the capabilities of its Intelligent Illuminator system. According to Tomoyuki Matsuyama of Nikon, it is not sufficient to have a thousand or so tip-able mini-mirrors to properly tailor an illumination pupil. Rather gray-scaling is needed, with 10,000 to 100,000 “degrees of pupilgram freedom” required to properly match the OPC signatures of tools. Such a capability optimizes the process window in SMO, according to Matsuyama, who did not discuss Nikon hardware or when it would be available. Other symposium participants averred that hardware did exist (at least as a prototype) and had been described privately to potential customers.

Nikon was much more forthcoming about its “quick reflex” adaptive mirror which uses actuators on the mirror in the NSR-620D 193i stepper to correct for thermal and other aberrations of the imaging system. According to Jun Ishikawa of Nikon, the mechanical actuators allow near-instant correction of important aberrations using Nikon’s CDU Master analysis system. Dynamic lens control during a scan improves mix-and-match overly and corrects for distortions.

The ASML FlexWave is a plate with local heating and cooling elements that can correct Zernike aberrations Z5 through Z64, which improves the overlapping process window, overlay, and throughput of the XT:1950i, according to Frank Staals. This capability is needed, for example, when widely different illuminations are applied to different layers of a chip printed on the same tool. There is some increase in flare, he admitted, but well within specs. Throughput can be increased to 250wph if corrections do not need to be constantly updated.

Both vendors touted increased throughput of their top-of the line immersion systems and claimed <2nm overlay performance to allow for 32nm production. However, two papers described how single exposure technology could be substituted for double at difficult 32nm and 28nm contact layers. The key trick appears be altering the design to use larger combined geometries where the electrical function and imaging allow, and optimizing the masks for that target. Henning Haffner of Intel suggested that the design community needed a mask optimization tool that would replace an engineer’s intuition for that task.

Design for Manufacturing Doubles Down

The frontier in design process integration is now clearly DP, especially for logic. Since there are two distinctly different DP paradigms (SADP and LELE), designers and software developers are torn. Both have paradoxes and chip failure mode liabilities, according to Yuangsheng Ma of GlobalFoundries. Some design features may have to be abandoned; routers and placement tools will need to be aware of DP prohibitions. With care and the use of the block layer to define SADP features, the methods explored for memory can be adapted to logic, reported Ma.

Lars Liebmann of IBM was not so sanguine. He warned that industry-wide standards need to be developed for DP or it will “fail” the way alt-PSM “failed.” Only this time, there may not be an economical alternative for continuing Moore’s Law in most of the industry. Liebmann explained that 80nm was really the final pitch limit for single exposure with water immersion technology and it will be reached at the 22nm node in 2012. Then what? Restrictive resign rules (RDR)? Decomposition-aware design rule checking (DRC)? The industry must decide, and then develop tools that can report actionable errors to designers as well as transmit the “color information”-the multiple patterns needed for a single mask layer-downstream from standard cell libraries to placement tools and routers in the EDA flow.

Liebmann advocated a strategy of “anchored coloring plus smart placement” to avoid conflicts while minimizing area increase. The coloring on one level requiring double patterning affects the layout on the next, which then affects the coloring and so on. Liebmann predicted that the 20nm node would require 3 levels of DP, and that 14nm would require 7 levels of DP with at least one triple-patterned layer thrown in! We really must hope that EUV or EbDR will work efficiently soon enough, so that designers do not have to chase coloring conflicts through 7-8 layers to build chips selling for a few dollars for a few months in not many years from now! – M.D.L.

Friday, February 25th, 2011

After successful high-volume manufacturing (HVM) beta-site evaluations, EV Group (EVG) has released an automated mask aligner fine-tuned to maximize yield in high-brightness LED (HB-LED) fabs. The EVG620HBL upgrade to the 620-platform creates an automated tool that can align and expose 165 wafers/hour, with new illumination optics that can easily see alignment marks on the transparent sapphire substrates commonly used for GaN-epi today (figure). New to this tool are five cassette stations – significantly more than competitive offerings – to enable continuous fabrication of devices at up to 220 wafers per hour in first print mode for substrates up to 150mm diameter.

HB-LED GaN-epi on sapphire marks, (LEFT) with conventional illumination, and (RIGHT) with new illumination in EVG620HBL tool. (source: EV Group)

HB-LED GaN-epi on sapphire alignment marks, (LEFT) with conventional illumination, and (RIGHT) with new illumination in EVG620HBL tool. (source: EV Group)

EVG claims that its bonders and mask aligners are being deployed by four of the top five major HB-LED manufacturers, and that customers drove the creation of the 620HBL to increase their line yields and throughputs. Since the next major market for HB-LEDs is general lighting, cost reductions in high-volume manufacturing (HVM) are critical if CFLs and other general purpose lighting technologies are to be replaced. Throughput is critical for overall cost-reduction, to be sure, but yield losses probably dominate cost-of-ownership (CoO) considerations in evaluating competing fab tools.

Typical HB-LED process flows include 4-5 mask steps, and misalignment between masks is a major factor in yield loss. This new aligner now includes special recipe-controlled microscopes with illumination spectra and polarization optimized for pattern contrast with various wafer and layer materials. It is dedicated to high-brightness LED on sapphire, but it can be used equally well with other substrates such as silicon carbide (SiC), aluminum nitride (AlN), other ceramics, or even metal.

EVG620HBL mask aligner (source: EV Group)

EVG620HBL mask aligner (source: EV Group)

Basic tool capabilities include the following:

  • Wafer diameters: 50-150 mm, changeable in <1 minute
  • Substrates: Sapphire, SiC, Si, AlN, metal, ceramic
  • Throughput: max.165 wph (aligned), 220 wph (first print)
  • Top Side Live Alignment Accuracy: +/- 1.0 micron
  • Bottom Side Alignment (option): +/- 1.5 micron
  • Exposure: Proximity, Soft-, Hard- and Vacuum-contact
  • Pattern resolution: 2.0 micron (Proximity)
  • Footprint: 2.1 m2 (figure)
  • SECS II/GEM interface : optional

“Just last month, one of the leading HB-LED manufacturers ordered an EVG560HBL bonder,” stated Paul Lindner, EVG’s executive technology director, “and the EVG620HBL is the latest result of our ongoing efforts around enabling HB-LED manufacturers to develop more efficient, cost-effective and higher yielding devices to meet their customers’ demands. We look forward to making further inroads with this latest offering, which also features high-accuracy handling and alignment of fragile or warped wafers.”

In an exclusive interview with BetaSights, Thomas Uhrmann, EVG’s business development manager, explained how the quick-swap (<1 min.) vacuum chucks allows for HVM compensation of the different inherent bows of different epi-wafers. Though the tool can function in contact- and vacuum-modes, proximity-alignment of tens of microns is almost always used to extend mask life and reduce particles in patterning HB-LEDs.

For 150mm-diameter sapphire wafers, the thickness spec. today is 1.0-1.3mm. However, once GaN epi-layers are grown using MOCVD, the mismatch between substrate and epi Coefficients of Thermal Expansion (CTE) always induces stress and warp. A typical process flow to grow the epi stack involves several hours at ~700°C to grow the buffer layers, followed by ramp to ~1050°C to grow the multi-quantum well (MQW) and p-GaN layers. As the wafer is heated and then cooled, the CTW-mismatch first creates compression and then tension in the epi layers. EVG’s applications engineers reportedly see up to a full 1 mm of warpage in GaN-epi on sapphire wafers at room temperature.

Since an LED’s color is determined by the composition of the epi-layers, and since different epi-layers with have different CTEs, epi-wafers to produce different LED colors will have different extents of bow. Consequently, a HVM LED fab can use this new tool with a different chuck for each product to ensure optimal wafer flatness during proximity alignment.

There seems to be one big variable in the world of GaN-epi growth: the possibility of homo-epitaxy on GaN substrates. Since control of defects is critical for GaN device functioning, and since hetero-epitaxy always induces defects, going to homo-epitaxy offers inherently superior device performance. The ability to use simple back-contacts saves fab costs, too. If UCSB spin-out Inlustra Technologies can ramp up 50mm diameter GaN substrates and offer them at reasonable prices this year, then sapphire might start to give way as the substrate of choice for HB-LED HVM. However, since GaN is itself rather transparent, the new EVG aligner seems like an ideal tool for HB-LED patterning. -E.K.

Friday, January 7th, 2011

IEDM 2010 provided extensive details of the near term evolution of mainstream IC memory technologies DRAM and NAND Flash. There were many other presentation on up-and-coming memories like phase-change memory (PCM) and resistive random access memory (ReRAM), but the relative newcomers are struggling to keep up with the moving targets in DRAM and Flash performance/cost capabilities.

Samsung uses Self-Aligned Reverse Patterning (SARP) for 2Xnm node Flash chips (source: IEDM2010, S05P01)

Samsung uses Self-Aligned Reverse Patterning (SARP) for 2Xnm node Flash chips (source: IEDM2010, S05P01)

Samsung researchers showed (S05P01) how evolutions of 3Xnm node NAND Flash processing can be made to work for 2Xnm node chips, and claimed that variability can be managed with lithography and annealing/oxidation to allow for 3-bits per cell. Sidewall spacer double-patterning (SSDP) will be used for 2Xnm half-pitch structures, but in a variation Samsung terms “Self-Aligned Reverse Patterning” (SARP) where the sidewalls define the pattern instead of the cores/spaces (figure). The CD uniformity of SARP is reportedly <5%, compared to >10% when trying to use the cores/spaces of “SADP,” and the improved uniformity reduces threshold voltage (Vth) distribution. An unexplained “novel tunnel oxidation” process was used to concentrate the implanted boron (B) near the silicon surface, resulting in a ~0.5V increase in the initial Vth along with lower junction leakage characteristics.

Intel/Micron researchers presented on (S05P02) “25nm MLC NAND Technology and Scaling Challenges,” showing a 64Gb multi-level cell (MLC) NAND with a cell size of just .0028um2, and with only 30-40 electrons separating logic-levels. Wordline material is not specified but is patterned using a subtractive flow. The number of electrons needed to induce a 100mV shift in Vt scales with reducing material volume, and electrons trapped in parasitic locations can be easily detrapped to show up as a charge loss mechanism. At the 25nm node, just a single electron at the wrong location can induce a 100mV shift (table)!

In nanoscale transistors the conduction through the channel is essentially filamentary, and the interaction of dopant atoms and interface states or traps causes channel conduction to be non-uniform. At 25nm, there are ~75 boron atoms/cell (with 50-100 as the +-3sigma range), and the Vt is expected to vary by ~30% purely due to random dopant fluctuation. In addition, noise is caused by a variable number of electrons tunnelingdue to quantum mechanical effectsduring each programming pulse, and since the number of electrons is reduced with scaling this random noise increases.

Circuitry tricks like the use of error-correction control (ECC) bits has been used to compensate for noisy memory cells, but as noise increases the number of ECC bits must also increase. At 25nm the circuit uses a 1KB codeword. However, there is a limit to the present ECC approach, and new algorithms may be needed.

TEM cross-section of a Flash memory cell showing ~4nm TaN floating-gate (FG) and hafnia-alumina-hafnia (HAH) inter-poly dielectric (IPD). (source: IEDM2010, S05P03)

TEM cross-section of a Flash memory cell showing ~4nm TaN floating-gate (FG) and hafnia-alumina-hafnia (HAH) inter-poly dielectric (IPD). (source: IEDM2010, S05P03)

Researchers from North Carolina State University (NCSU) working for Intel and the National Science Foundation (NSF) presented (S05P03) on the scaling limits of Flash memory cells. By properly engineering sandwiches of Hf-based high-k dielectrics in combination with TaN metal floating- and control-gates, scaling down to 1Xnm node was shown. Replacing the conventional oxide-nitride-oxide (ONO) dielectric stack with HfO2-Al2O3– HfO2 (HAH) (figure) or a single layer of HfAlO for the inter-poly-dielectric (IPD) lower band offsets and reduce gate-to-gate leakage.

A single layer of HfO2 crystallizes during the 450°C floating-gate anneal (FGA) such that grain-boundaries form to provide leakage paths. The alumina in the middle of the HAH stack remains amorphous post-FGA, so leakage was comparable to the HfAlO. However, Fowler-Nordheim modeling predicts that the electron tunneling distance for HAH will be longer than HaAlO for the same physical thickness, so leakage should be reduced using the stack.

Process Flow:

  • n-Si substrate

  • Tunnel ox by furnace (7nm SiO2),

  • FG by PVD (10nm TaN),

  • IPD by ALD,

  • CG by PVD (10nm TaN).

Scaling of the TaN FG (tried 10nm, 4nm, and 1nm) while maintaining the same HAH IPD. Program-erase characteristics shown well down to 1nm thickness! Endurance tests showed no changes from 10nm to 4nm, but 1nm showed Vfb shift while the PE characteristics were maintained.

eDRAM for 3Xnm node ICs

Renesas' capacitor in porous low-k (CAPL) eliminates W bypass contacts for reduced eDRAM delay (source: IEDM2010, S33P03)

Renesas' capacitor in porous low-k (CAPL) eliminates W bypass contacts for reduced eDRAM delay (source: IEDM2010, S33P03)

Renesas researchers presented (S33P03) on, “A novel cylinder-type MIM Capacitor in Porous Low-k Film (CAPL) for Embedded DRAM with Advanced CMOS Logic.” A paradigm shift is occurring for embedded DRAM (eDRAM) using traditional capacitor over bitline (COB) structures: the tungsten (W) bypass contacts (BCT) to transistors where there are no metal-insulator-metal (MIM) cylinders (figure) now induce excessive circuit delays. The BCT induced delay has been simulated to slow down the circuit by ~10% in 4Xnm node circuits, and the delay only increases in 3Xnm node structures. To avoid the bypass contacts, the MIM cylinder could be built into the interconnect layers, but would be challenged by the pores of advanced low-k dielectrics used in interconnects today.

Renesas' capacitor in porous low-k (CAPL) eDRAM structure requires careful control of the etch process to provide smooth sidewalls with a bottom angle of ~88° for void-free filling. (source: IEDM2010, S33P03)

Renesas' capacitor in porous low-k (CAPL) eDRAM structure requires careful control of the etch process to provide smooth sidewalls with a bottom angle of ~88° for void-free filling. (source: IEDM2010, S33P03)

Using SiOCH molecular pore stacking (MPS) low-k dielectrics with average pore size of 0.4nm as part of the interconnect, the etch process must be carefully tuned to provide smoothly tapered sidewalls (figure). Low-k films with larger pore sizes allowed for metal precursor penetration into the dielectric with serious performance degradation, while 0.4nm pores could withstand exposure to a Ti precursor for a ”surface-reaction controlled CVD” process (pseudo-ALD) followed by NH3 exposure to form TiN as the bottom electrode. Then so-called “CVD” of ZrO2 and TiN completes the MIM structures, with capacitances reportedly ~8 fF/cell. Capacitance ~11fF/cell could be realized by extending the CAPL structures up through an additional metalization layer at the same pitch (~40 nm MIM pitch @ 3Xnm node). Reliability of the MPS has been characterized, including a Vbd of ~2.7 V which is greater than the operating voltage.

So eDRAM technology—like stand-alone DRAM—can be extended to smaller geometries by the use of ALD to provide conformality in forming MIM stacks inside of extremely high aspect-ratio (AR) structures. Before deep-trench DRAM was killed a while back, up to 80:1 AR structures had been proven as manufacturable using ALD. So, it looks as if the industry workhorse memory that is DRAM is still extendable to 2Xnm nodes and perhaps beyond, while NAND Flash looks good down to 12nm geometries. Other memory technologies will probably remain relegated to niches for the near term. E.K.

Tuesday, December 21st, 2010

Graphene—the 2D hexagonal lattice of carbon—has been under investigation as a new material for electronics applications due to it’s high mobility and other unique properties. At IEDM this year, an entire session (#23) was devoted to showcasing graphene devices, and to sharing the latest processing tricks to grow and (sometimes) transfer the single-atomic-layer of carbon to an oxidized silicon wafer. High-speed analogue (RF) circuits have been shown by IBM, SAIT, and MIT, and IBM has created a 130 meV bandgap with ~400 meV predicted as possible. Outside of IEDM, GeorgiaTech has published on how to form 10,000 top-gated graphene transistors in 0.24 cm2 of SiC chip area.

IBM's dual-gated bi-layer graphene device structure (source: IEDM2010)

IBM dual-gate bi-layer graphene device sideview (source: IEDM2010)

IBM researchers in Yorktown Heights, NY (S23P01) presented an invited paper on graphene applications, including discussion of how to form a bandgap in bilayer structures that allows for the creation of optoelectronic devices and possibly even digital circuitry (figure). These bilayers have a four atom unit cell, hyperbolic dispersion, and no intrinsic bandgap. However, the application of a strong perpendicular electric field produces an asymmetry by inducing charge transfer between the layers.

Using dual-gated (top and bottom) graphene field-effect transistors (GFET) with an NFC/HfO2 gate stack, field-tunable bandgaps of more than 130 meV were created, with on/off ratios of ~100 at room temperature and >1000 at low temperatures. Although this small gap is still not sufficient for digital devices, it could be used in optoelectronic applications such as THz emitters and detectors. With improvements in both the graphene and dielectric quality, a bandgap of ~400 meV has been predicted to be possible.

A sophisticated photodetector can be fabricated using bilayer graphene. Multiple inter-digitated electrodes are made using two metals with different workfunctions: Pd and Ti have been shown. At appropriate backgate biases, the different workfunctions and resulting asymmetric band-bendings generate a sloping overall potential along the graphene channel that allows photodetection over the entire device. This type of device was tested and found to be able to reliably detect optical data streams of 1.55 micron light pusles at a rate of 10 GBits/s (maximum capability of the measurement system) without an applied source-drain bias.

Columbia U.'s BN top-gate for graphene (source: IEDM2010)

Columbia U.'s hexagonal-BN gate for graphene structure (source: IEDM2010)

Columbia University researchers (S23P02) used exfoliation of single-crystal hexagonal boron nitride (h-BN) as the gate under exfoliated graphene to create FETs with mobility values exceeding 10,000 cm2/V•sec and current saturation down to 500 nm channel lengths with intrinsic transconductance (gm) values above 400 mS/mm (figure). Because the h-BN can be made arbitrarily thin (down to a single monolayer), the same h-BN dielectric layer can function as both a supporting substrate and the local-gate dielectric. Top ohmic contacts were made using Cr/Au (1nm/90nm), producing p-type doping of the graphene under the contacts because of work-function differences.

Researchers from Seoul National University and Samsung Advanced Institute of Technology (S23P05) reported on a similar graphene layer transfer technique onto oxidized silicon wafers with locally-embedded TiN back-gates to create RF devices. Despite underlap between the gate and the source/drain, researchers measured a record maximum mobility of 9000 cm2/Vs, with a general range of 3000-6000 cm2/Vs which allows for fT =80 GHz using 0.24micron gate lengths.

Despite these high mobilities, gm and Ids still remain low for various reasons associated with the R&D processes used on 150mm diameter wafers. Causes could include high contact resistance due to poor adhesion from lift-off process, impurities between the gate oxide and graphene channel from the graphene transfer, or contamination of the exposed graphene channel under ambient conditions.

MIT researchers discussed (S23P06) how the unique ambipolar transport properties of graphene, combined with its high mobility at room temperature, enable the development of a new form of non-linear electronics for radio frequency (RF) and mixed-signal applications.

Single-layer graphene films can be grown by CVD on sacrificial copper substrates. Firstly, copper foils are annealed at 1000°C in H2 (350 mTorr for 30 minutes) to increase their grain size, then they are exposed to low-pressure (1.6 Torr) CH4 to initiate large poly-crystalline graphene growth (80 x 80 micron plan-view of a single-crystal shown). Next, polymethyl-methacrylate (PMMA) is coated on the graphene film and the copper substrate is etched away. Finally, the graphene is transferred onto polished Si wafers with a 300nm thermally-grown SiO2, where Hall effect measurements show mobilities in the 1800-2500 cm2/Vs range.

MIT's graphene on insulator FET formed by layer-transfer from from a sacrificial Cu-foil (source: IEDM2010)

MIT's graphene on insulator device formed by layer-transfer from a sacrificial Cu-foil (source: IEDM2010)

Ohmic contacts are formed by depositing a 2.5nm Ti/45nm Pd/ 15nm Au metal stack by e-beam evaporation. Device isolation is achieved by O2 plasma etching. The gate dielectric consists of 5nm of e-beam evaporated SiO2 as a seed layer, followed by 15nm of ALD Al2O3. The top gate is formed with a 30nm Ni/ 200nm Au/ 50nm Ni metal stack (figure).

For frequencies >400GHz, the presenter mentioned that efficiency is often <20% for today’s frequency multipliers. In stark constast, this graphene device shows the ability to double a 700 MHz input to 1.4GHz output at room temperature with >90% of the output power, and without the need for any filtering elements. The high quality of graphene devices could thus allow for more efficient analogue and mixed-signal circuits, since each filter is a source of noise and loss. Potential security and medical screening applications would use 0.3-10 THz frequencies that can pass through fog, fabrics, plastics, and bricks. Theoretically, graphene devices could be used for power gain, though no one has yet shown such function.

A team from IBM and MIT (S09P06) demonstrated RF performance of sub-100nm graphene transistors fabricated using epitaxial growth on a SiC substrate. A cut-off frequency as high as 170 GHz is achieved in a 90nm graphene FET using NFC/HfO2 as the top gate dielectric, and e-beam evaporating 20nm Pd/30nm Au as the contact metal.

Modeling of gm by varying Rs for 70 nm and 1 ?m devices and the improvement of projected fT. (source: IEDM2010)

Modeling of gm by varying Rs for 70 nm and 1 ?m devices and the improvement of projected fT. (source: IEDM2010)

Transconductance (gm) can be improved by 4 times for a 70nm device by reducing the contact resistance, which is much greater effect than in the long channel case (figure). A 90nm-gate graphene FET showed a cut-off frequency as high as 170 GHz at a drain voltage of 2.2V. The device performance is limited by the series resistance, including the contact resistance and the access resistance associated with ungated region. Consequently, the researchers model that the cut-off frequency can be enhanced to as high as 350 GHz using a self-aligned gate structure.

Outside of IEDM

Outside of IEDM this year, Georgia Tech folks recently published work in Nature Nanotechnology on the preferential epi growth of graphene nanoribbons on the sidewalls of properly oriented silicon carbide recessesses. Structures are formed using photolithography and etching. Pre-epi, the wafer is heated to ~1,500°C to melt and polish any rough edges left by the etching, so as to avoid electron-scattering. These prototype graphene devices exhibit a weak on:off ratio of 10, with carrier mobilities up to 2,700 cm2/Vs at room temperature. However, while dependent upon SiC as the substrate instead of Si, this approach has already allowed for the fabrication of 10,000 top-gated graphene transistors in 0.24 cm2 of SiC chip area, claimed as the highest density of graphene devices reported to date.

Though all of this is still far away from commercial manufacturing, the fact that epi-growth and layer transfer of graphene has been shown to produce highly functional devices is an indication that we are headed in the right direction. Potential applications have been shown for high-speed analogue circuits and novel light sensors. E.K.

Tuesday, December 14th, 2010

TSV are finally finding problems to solve. As previously covered by BetaSights, through-silicon vias (TSV) for 3D circuit stacking will first be used in silicon-interposers (formerly known as silicon-substrate multi-chip modules, “Si-MCM”), as indicated by Xilinx’s announcement of high-end FPGAs requiring the nascent technology. Now IBM has teamed with Semtech to announce plans for a new silicon-interposer ADC/DSP product family that has applications in fiber optic telecommunications, high performance RF sampling and filtering, test equipment and instrumentation, and sub-array processing for phased array radar systems.

Semtech (the analog and mixed-signal IC company) is partnering with IBM to develop an end-to-end module solution using IBM’s 3D interposer technology to interconnect ADC functions in IBM custom logic SOI-based Cu-45HP technology with interleaver ICs in IBM’s 8HP BiCMOS SiGe technology. These two different technologies are connected through a single wiring layer on an interposer, which supports a bandwidth of greater than 1.3 Tbps in this design. Semtech will have first ADC/DSP prototype modules available in 2011 and are working with partners to extend these product offerings utilizing these technology elements.

(IBM's silicon-interposers using Cu TSV along with deep trench capacitors (source: BusinessWire)


IBM’s 3D technology combines cost effective 90nm BEOL wiring levels with copper (Cu) TSV (figure). The fact that IBM is now on-the-record as using Cu TSV for production is surprising and may be a classic example of technology mis-direction, since most of the previously published papers on TSV technology development by the corporation used tungsten (W) metal instead of Cu. IEDM this month included a presentation by IBM and National Chiao Tung University titled, “Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding.” Of course, the W TSV are supposedly intended to go through dice with active circuitry, while the Cu TSV are so far only announced for interposers.

Regardless of the via metal, integrated passive components provide superior performance in system-in-packages (SiP) using silicon interposers. IBM has developed the ability to provide ultra high capacitance density by integrating deep-trench (DT) capacitors at the top surface of the interposer. As frequency increases, the use of integrated decoupling capacitors is more attractive to counteract power supply noise effects that typically may be second order issues for slower applications.

“3D technology provides a path to integrate CMOS and SiGe technology at very high bandwidth and with low power to provide a seamless high-performance module solution,” said Dan Berger, IBM Manager of 3D Technology Development at its Semiconductor Research and Development Center (SRDC). IBM’s semiconductor, wafer finishing and assembly facilities offer a one-stop module solution for Semtech and its product partners. We also see significant benefits using 3D technology for other applications to address issues such as I/O power, power supply, interconnection bandwidth between components, modularity for re-use of IP or mixing technology nodes effectively, and form factor improvements that can be obtained by integrating components together in a smart cost effective manner.”

IEDM 2010 TSV updates

Since the recently concluded IEDM in San Francisco placed more emphasis upon “More-than-Moore” technologies, there were two sessions covering 3D including TSV. Session 2 was titled, “Process Technology – Advanced 3D Integration,” while a special invited session (#17) was on the, “Confluence of Technology and Design – Challenges for Non-Conventional Devices and 3D LSIs.”

Schematic of the gate stack under test and the main technology options implemented in our 300mm High-k/ Metal Gate First CMOS 3DIC via middle baseline. CMOS is done until contact level then the Cu-TSV module is inserted, followed by BEOL. (source: IEDM2010, Session2.1)

Schematic of the gate stack under test and the main technology options implemented in IMEC's 300mm High-k/ Metal Gate First CMOS 3DIC via-middle baseline. CMOS is done until contact level then the Cu-TSV module is inserted, followed by BEOL. (source: IEDM2010, Session2.1)

IMEC researchers used a via-middle Cu TSV process flow to examine the Keep Out Zone (KOZ) requirements for active circuitry (figure). TSV induced stress changes with temperature as the tensile copper expands faster than silicon when heated. The TSV KOZ is expected to disappear at the stress-free Cu temperature of 145°C. The researchers experimentally demonstrated a significant influence of TSVs on adjacent transistors, with up to 30% Idsat shift due to TSV stress. The KOZ for a large matrix of TSVs is over 200 microns for analog circuits and 20 microns for digital circuits (figure). The complex interactions of stress components makes it difficult to use simple design rules without sacrificing large layout areas. The issue of induced stress and uncertainty in active circuitry KOZ rules is only one of the reasons that TSV are today only designed into passive interposers.

Keep out zone for analog devices with 0.5% delta-Ion sensitivity threshold and for digital devices with 5% delta-Ion sensitivity threshold as a function of the number of TSVs in the matrix. (source: IEDM2010, Session2.1)

Keep out zone for analog devices with 0.5% delta-Ion sensitivity threshold and for digital devices with 5% delta-Ion sensitivity threshold as a function of the number of TSVs in the matrix. (source: IEDM2010, Session2.1)

The first presentation in the reliability session (#35) covered research led by CEA-Leti on, “Investigation on TSV impact on 65nm CMOS devices and circuits.” Using 4 micron diameter Cu TSV, they ran electrical tests on isolated MOSFET transistors as well as on ring-oscillators. Noise spikes of 7uA/um were reportedly observed in the static source current of nMOSFETs at 5 microns distance; this corresponds to ~1% fo the saturation current. However, no mobility degration was observed in the ring oscillators. E.K.

Monday, November 29th, 2010

Rarely does the IC fab world see a really new tool. The shear complexity of multi-million dollar tools automated for high-volume manufacturing (HVM) means that changes are usually gradual and evolutionary. Today, Applied Materials officially announces the new “Centris” higher-throughput platform for etch, targeting formation of transistor as well as the sacrificial structures needed in sidewall-spacer double-patterning for lithography.

Schematic of the new Centris platform for AdvantEdge MESA etch chambers (source: Applied Materials)

Schematic of the new Centris platform for AdvantEdge MESA etch chambers (source: Applied Materials)

From a first glance (figure), Centris for etch is modeled on the company’s Producer platform for deposition, with a dual-blade robot handling wafers to and from parallel chambers. The new platform deals wafers to AdvantEdge MESA chambers that have previously run on the Century platform (>1500 AdvantEdge chambers shipped since 2001, and >200 MESA chambers in the first 9 months of release). When fully loaded with 6 etch chambers, the tool is claimed to be able to process 180 wafers-per-hour.

Each of the chambers in a set of two has separate high-vacuum pumps and gas delivery sub-systems, allowing process recipes previously developed for MESA chambers to be run on the new platform. However, each set of two chambers shares heat-exchangers, roughing pumps, facilities gases, and cooling water to reduce costs and fab floor space. Compared to Centura MESA etch processes, the company targets a 30% reduction in the cost-of-ownership (CoO), with ~1/3 of that (or ~10%) derived from energy savings alone.

Significant new sub-systems in the Centris platform include the following:

  • Bromine-abatement integrated into the load-lock,

  • Four FOUP interface, and an

  • Optimized gas panel for chamber matching.

The new gas distribution sub-system includes all lines to chambers of equal length (for chamber matching), and the ability to share a single input manifolded to six. However, the degree of control needed for 32nm node etching is such that the best designed sub-systems will still experience parameter drifts during manufacturing. As such, periodic sub-system calibration to some reference standard is now part of standard fab routines, and this new tool automates the calibration process. A mass-flow standard (with rate of rise) and a manometer are integrated into the hardware platform, and software automatically trigger calibrations during chamber during down-times. In an exclusive discussion with BetaSights, Thorsten Lill, Applied Materials’ vice president of the Etch Business Group, stated that the chamber base pressure repeatability using auto-calibration was within the range of 0.1 mTorr.

“Conductor etch” is one of the fastest growing IC fab OEM segments. In part due to the challenges of forming new transistor and isolation structures (figure), but also due to double-patterning (DP) and hard-mask etch falling into this categorization. While some manner of DP will be used for many critical layers at the 32/28nm node, there are still many variations on the theme. Even within a general process flow like sidewall-spacer DP, there will be sub-variations. Even within sub-variations, the process window is so slight that there probably will be no “universal patterning” flow that works for all layers. “In reality, you see slight tweaks for dense-iso requirements,” explained Lill. “For example, you could have a scheme where two spacers are too close.” Each fab chooses the detailed DP flow based on differences in the material layers to be patterned, as well as on the legacy tools running in the line.

SEM cross-section of NAND STI structures etched using double-patterning and the MESA Pulsync technology to minimize micro-loading (source: Applied Materials)

SEM cross-section of NAND STI structures etched using double-patterning and the MESA Pulsync technology to minimize micro-loading (source: Applied Materials)

For almost any double-patterning approach, etch now provides the most essential control of the patterning. As such, the post-process critical dimension (CD) variation must be minimized though both control and matching of chambers. A 4000 wafer run of 40nm test-element groups (TEG) through 4 chambers on a Centris reportedly demonstrated 0.8 nm range.

In other etch news, the company has also released a new “ultra” high-density plasma (HDP) Silvia chamber for the Centura platform, primarily targeting through-silicon via (TSV) formation. The company claims a 40% higher etch rate with the new source. —E.K.

Friday, November 26th, 2010

On November 16 of this year, the IEEE San Francisco Bay Area Nanotechnology Council held a symposium on nanomanufacturing that included presentations by TSMC and GlobalFoundries (GloFo) on gate-last (GL) versus gate-first (GF) high-k metal-gate (HKMG) integration. Control of non-visible defects (NVD) in manufacturing is vital, particularly for GF flows, and such control is provided by patterned wafer work-function metrology from Qcept Technologies (figure), though this newer metrology capability was not discussed during the IEEE event.

ChemetriQ 5000 patterned wafer work-function metrology tool. (Source: Qcept Technologies)

ChemetriQ 5000 patterned wafer work-function metrology tool. (Source: Qcept Technologies)

One of the biggest technology issues in commercial IC fabs today is how to integrate HKMG CMOS transistors at the smallest geometries. As previously covered by BetaSights, Intel and TSMC have chosen GL integration for the 3Xnm node, while GF has been chosen by IBM and GloFo and the rest of the world (except for UMC using both GF and GL).

The benefits of the GL (a.k.a. replacement metal gate or RMG) flow were presented by Di Ma, vice president of field technical support for TSMC North America. TSMC’s variant of the 32/28nm node uses HKMG for high-performance CMOS, while the foundry still provides traditional SiON/poly-gate CMOS for low-power chips. Restricted design rules (RDR) are definitely needed at this node.

It is universally acknowledged that the GF flow is derived from traditional SiON/poly-gate flows, while GL requires integration in new directions. “After thorough evaluation, TSMC has decided to take on the gate-last integration challenges,” explained Ma.

According to Ma, there are 5 basic advantages of GL over GF that justify the integration investment:

  1. Faster ICs (mostly on the PMOS side),

  2. Lower power (lower Vt allows lower Vcc),

  3. Higher yield (reduced NVD issues),

  4. Reliability (no high-temperatures post-gate),

  5. Forward compatibility (more MG options for shrinks).

“I’m an old-timer,” said Ma, as he explained the history of commercial MOSFETs starting with NMOS poly up to today’s CMOS HKMG. Regarding the HKMG flow choice for the 32/28nm node, Ma asserted that the industry would, “probably have to use gate-last by 22 or 20 nm anyway.” Forward compatibility is helped by greater flexibility in being able to tune the work-function of metals after all the highest temperature processing of oxides and nitrides.

Ma said that 28nm SiON/poly has passed full qualification at TSMC, and that 28nm HKMG is now “on track.” The company claims to have already engaged with 40 customers for 28nm node ICs, with first production tape-outs in this quarter, and 50 tape-outs expected in 2011. However, Ma did not specify the split between SiON/poly and HKMG for all of these ICs.

ChemetriQ charge map of a 45nm node GlobalFoundries CMP wafer from a malfunctioning cleaning tool. The dark blue region at the center was charged to -4.5V, which was sufficient to cause yield loss of all the dice in that region. Prior to this charge map being generated, GlobalFoundries had taken this tool offline because of the yield issue with no correlating defectivity reported by optical inspection tools used at the fab. (Source: Qcept Technologies)

ChemetriQ charge map of a 45nm node GlobalFoundries CMP wafer from a malfunctioning cleaning tool. The dark blue region at the center was charged to -4.5V, which was sufficient to cause yield loss of all the dice in that region. Prior to this charge map being generated, GlobalFoundries had taken this tool offline because of the yield issue with no correlating defectivity reported by optical inspection tools used at the fab. (Source: Qcept Technologies)

“If there are defects in electrical parameters they are difficult to find until the very end of processing,” reminds Ma, explaining why TSMC prefers to take on the known visible defects associated with GL. Proven technology to defect NVD may not have been available when TSMC had to choose it’s integration scheme, but such capability has existed since this summer when Qcept released the ChemetriQ5000 tool to provide work-function measurement on patterned wafers (figure).

Nick Kepler, GlobalFoundries vice president of corporate program management, summarized the good reasons to choose GF HKMG for the next node:

  1. Backwards compatibility (to SiON/poly), and

  2. Design flexibility (fewer restrictions needed).

“First of all, when we introduce new materials we look at how to make the change as simple as possible to minimize risk,”explained Kepler. “The gate-first implementation is the most similar to polysilicon. The second is we wanted to put as few constraints as possible on the design teams. With gate-first we can allow for things like bi-directional poly, poly jogs, and large caps.” Kepler claimed that such design flexibility allows GloFo to get to 20-25% smaller overall die size compared to GL.

However, when you compare GloFo’s 32nm relaxed designs with TSMC’s more aggressive shrink to 28nm restricted designs, the area results are probably about the same. Kepler also reminded the audience that GF flows allow for significant Vt tuning through the use of monolayer oxides, and that GloFo offers multiple Vt levels to it’s customers.

If GF and GL flows provide similar die sizes with similar overall circuit performance, the main difference may be in the yield numbers, and fab yield is controlled by metrology and inspection tools. Last summer, following successful beta-site evaluations at an unnamed fab, Qcept announced the first sale of a ChemetriQ5000 tool capable of patterned wafer NVD inspection with 0nm edge-exclusion. In a meeting with BetaSights in July of this year, Qcept vice president of marketing Ralph Spicer explained that this new tool uses a ~30 micron diameter sample area with a continuously rotating stage to provide ~15 wph throughput. –E.K.