The IC fab industry is notoriously conservative, and normally abstains from risky behavior like contracting new processes. Still, there are times when what we’ve been doing no longer satisfies today’s needs, and we have to try something new. Both Novellus Systems and Applied Materials have recently announced new vapor deposition (VD) tools and integrated process recipes for silicon-oxide dielectrics, after many successful beta-site evaluations by customers. Both technologies create oxide films for 32nm and 22nm node device structures: transistor isolation, various integrated and sacrificial spacers, and sidewall spacer double patterning (SSDP) lithography. Both claim the ability to form “furnace-quality” films, with conformality somewhere between chemical-vapor deposition (CVD) and atomic-layer deposition (ALD).

CFD

SEM cross-sections of Conformal Film Deposition (CFD) into trenches. (source: Novellus Systems)

Novellus Systems’ multi-station sequential processing (MSSP) PECVD Vector platform gets an upgrade to a new conformal film deposition (CFD) process capability. The company claims 100% step coverage on structures with aspect ratios (AR) of up to 4:1. The company shows SEM cross-sections of ideal trenches for deposition (smooth sidewalls <90°) that are nearly perfectly filled (figure). Such capability could meet 22nm requirements for front-end-of-line (FEOL) applications such as gate liners, spacers, and shallow trench isolation (STI), as well as the spacers that will be used for much of the world’s sidewall spacer double patterning (SSDP) lithography in the future.

CFD technology forms highly conformal films for FEOL applications, doing so at low temperatures to meet the requirements of 22nm node devices. CFD can run <300°C for Flash isolation, and as low as 50°C for direct deposition on photoresist for sidewall spacer double patterning (SSDP) lithography. FTIR spectra and current-voltage plots show that the film behaves like a thermal oxide, and film quality on sidewalls reportedly matches that in the field.

As explained in the recent BetaSights post “Steady as she goes: optical lithography,” due to both delays and projected costs of post-optical lithography, the IC industry is using sidewall spacer double patterning (SSDP) schemes for 32nm node memory and 22nm node logic devices. Applied Materials has been touting the line-width roughness (LWR) healing power of it’s advanced patterning film (APF) for over a year, and so the company would rather deposit the sidewalls onto APF, and APF allows for relatively higher temperature processing. Novellus instead reminds us that the most cost-effective SSDP schemes use a photoresist core.

The thickness range of the CFD film is less than 0.2%, which is <0.1nm on a typical 30nm thick film. “CFD technology offers a breakthrough in the deposition of low temperature dielectric films with quality equivalent to a furnace deposition,” said Kevin Jennings, senior vice president of Novellus’ PECVD Business unit. “As device dimensions shrink beyond 32nm, films deposited using CFD technology will be required for multiple applications.”

Novellus is trying to keep most aspects of the process secret. In response to questions by BetaSights about CFD, the company would only acknowledge that plasma is involved in the process. The precursor is secret, but is “used in semiconductor fabs already,” and there was no exclusive precursors-supplier partner involved in the development.

In comparison to competitive spacer films formed using ALD, Novellus claims that the combination of CFD technology and the Vector MSSD architecture delivers significantly higher throughput and lower chemical consumption. The ALD process of record (POR) for spacers, may be a batch process developed by TEL using furnace ALD intellectual property (IP) acquired from ASM at the end of 2008. The TEL “Telindy Plus” is designed for 32nm node and below IC fabrication, using a 125-wafer batch size and high-speed robotics to oxidize and deposit many different films. The Telindy Plus reportedly handles the ALD step in TEL’s announced quadruple-patterning sidewall spacer lithography flow, though it can also operate in CVD and hybrid CVD/ALD modes for standard SSDP.

FCVD

Applied Materials' “Eterna” flowable CVD (FCVD) dual-chambers, not showing the many sub-system changes from prior PECVD Producer chambers. (source: Business Wire)

Yesterday, Applied Materials released a flowable CVD (FCVD) process running in new PECVD “Eterna” chambers on the Producer dielectric deposition platform (figure). Targeting 32nm node and beyond ICs with >30:1 AR structures, the FCVD process completely fills gaps from the bottom up with a dense carbon-free silica glass. The FCVD oxide gap-fill process uses secret process chamber sub-systems and a mysterious carbon-free silicon-precursor.

The company says that the chamber had to be significantly re-designed to handle the unique recipe requirements of the precursor and the “flowability.” Standard PECVD chambers reportedly fail in trying to produce FCVD films. “We had to do some unique hardware designs to allows this precursor to go on to the wafer, fill gaps, and leave no carbon in the final film,” said Bill McClintock, Applied Materials’ vice president and general manager of dielectrics and CMP. Consequently, even though it is only matter of time before word leaks out as to which precursor is used, McClintock is confident that OEM competitors will have difficulty in trying to clone the process.

Like Novellus’ CFD silica film, the Applied Materials FCVD silica compares favorably to thermal oxides in terms of density and electrical properties. Unlike the CFD, FCVD is touted as “the ultimate gap-fill dielectric” due to it’s ability to flow into and fill extremely re-entrant structures as narrow as 5nm without voids (figure). Initially targeting DRAM isolation, the FCVD process has past beta-site evaluations at six different end-user fabs for both memory and logic applications. “Every major memory customer has taken one of these,” said McClintock. “They are qualifying them for their major products, whether they be DRAM or NAND.”

Flowable-CVD (FCVD) provides bottom-up gap-filling with silica using a carbon-free precursor. (source: Applied Materials)

For 32nm node processing, the thermal budget for logic is ~400°C while that for NAND Flash is ~300°C. The basic process flow for any gapfill starts with liner deposition, then FCVD or SOG, then anneal(s), then CMP. The main advantage of FCVD over SOG is that a single FCVD anneal step replaces >10 SOG anneal steps. Applied Materials says that the CoO for 32nm node SOG gapfill is ~$20/wafer, with ~$5/wafer from the precursor cost alone. “We’ve worked with the chemical precursor supplier and the material cost per gram is about one-third of the precursor cost of SOG,” said McClintock. However, due to more efficient use of precursors in CVD compared to SOG tools, the actual cost-per-wafer for the FCVD precursor is hinted to be in the US$1.00-1.50 range.

In response to a question regarding the number of FCVD tools needed to support a high-volume fab, the company claimed that for a 22nm node Flash line running 120K wafer-starts-per-month (WSPM) a “couple of tools” would be needed to deposit a desired layer. If we assume 60K WSPM and 30 working days at 20 hours/day, then the throughput for a 6-chamber Producer would be 100 wafers/hour.

Possible FCVD precursors

Trying to pry “proprietary” information out of a technology executive these days is like trying to pull teeth on a roller-coaster: nearly impossible and always awkward. No OEM wants to talk about any real details today. Applied Materials will not say anything about the precursor molecule, oxidizer or possible catalyst used, continuous or pulsed flows, intermediate molecules formed for flowability, or annealing conditions. In private conversation with BetaSights during the official product launch in Santa Clara yesterday, McClintock provides only the single hint that, “The precursor never sees the plasma.”

Company executives have been careful to say that the precursor enters the chamber as a vapor, and initially deposits on the surface in a “liquid-like” manner to provide the great gap-fill. Then plasma is somehow used to transform the flowable material into a solid silica, perhaps in the presence of an oxidizer and/or a catalyst. The Eterna deposition chamber reportedly requires many unique sub-systems and will cost more than other Producer chambers. However, the company claims at least 50% improvement over SOG in terms of CoO for 32nm node and below gapfill.

We may speculate as to possible carbon-free silicon precursors by reviewing the latest catalog of off-the-shelf specialty molecules from established specialty materials suppliers. SAFC Hitech sells both trichlorosilane (“TCS”, SiCl₃H) and silicon tetrachloride (“STC”, SiCl₄). Air Liquid lists both hexachlorodisilane (“HCDS”, Cl₃Si-SiCl₃) and trisilylamine (“TSA”, Si₃H₉N). Online search reveals that Samsung filed for IP on HCDS for low-temperature conformal oxide deposition in 2002, specifying the use of a Lewis Base (such as pyridine or trimethylaluminum) as catalyst and H₂O vapor as reactant in a quasi-ALD sequence.

The only thing we know for sure is that Applied Materials claims sole ownership of the FCVD process, and that the process recipe comes free with the purchase of hardware as is standard with industry CapEx terms and conditions. The precursor is commercially available from a single-source today.

Previous FlowFill dielectric

During the Eterna launch event, ever-alert analyst Dean Freeman of Gartner/Dataquest asked about the comparisons between FCVD and the decade-old “FlowFill” dielectric that had been developed by Trikon. What is now part of the STS division of Sumitomo Precision Products (formerly Aviza, formerly Trikon) had failed to launch a flowable CVD dielectric oxide called “FlowFill” that was based on methyl groups. The product claim by Trikon for FlowFill—a “bottoms-up” dielectric fill for device isolation—was nearly identical to the current product claims for Eterna FCVD. The huge difference is that the latter film uses a carbon-free precursor and a more complex recipe to ensure that there is as little carbon as possible left in the final post-annealed material.

Why did FlowFill fail to win over major customers? Siemens reported in 1998 that the material demonstrated reduced reliability compared to SOG. LSI Logic worked with FlowFill, but then became a fabless company and the non-standard unit-process was not picked up but foundries. Perhaps the residual carbon contamination really was excessive, and there was no easy way to anneal it out. Perhaps it was just ahead of it’s time, since FCVD is now touted for 32nm node and below processing there was probably little pull from fabs to replace legacy CVD processes until now.

The future of IC fabrication seems to be more and more based on integrated thin-film depositions and etches (less and less based on simple 2D shrinks). Specialized new tools and materials are being developed to meet the precise needs of high-volume manufacturing. While the capabilities of legacy tools and processes continue to improve, inflection points routinely arise when something completely new suddenly wins the cost:performance tradeoff. With the introduction of CFD and FCVD for oxides, fab process engineers have new tools to use in creating ever more powerful and compact ICs. It is likely that the same tools can be extended to create SiON and SiN films, too. —E.K.

While “Sturtevant’s Law” (which states that optical lithography can make all the circuit structures needed for the next 7-10 years) still may apply, the real limits to any manufacturing technology are financial, not technical. The multiple patterning techniques contemplated for fabricating the next nodes are approaching financial unfeasibility (see BetaBlog post “Steady as she goes: Optical Lithography”). Ten years will take us to the 11nm node or beyond. To deal with this impending disconnect, the industry has been investing in various post-optical lithography schemes including extreme ultra-violet (EUV) illumination, e-beam direct write (EbDW), and nano-imprint lithography (NIL). Progress was reported for all these methods at SEMICON/West 2010, but none seemed about to triumph.

ASML getting ready for HVM with EUV

The leading candidate for next-node patterning continues to be EUV lithography (EUVL) using 13.5nm radiation. Hans Meiling of ASML reviewed the company’s extensive progress towards high volume manufacturing with the NXE:3100 EUVL system and follow-on designs. There are three of these NA=0.25 tools already built at ASML and 3 more being assembled. The first laser produced plasma light source has been attached to a 3100 exposure tool and “first light” (slit exposure) achieved.

ASML 2nd Generation NXE:3300B EUVL tool scheduled for first shipment early in 2012 (source: ASML)

Exposure power is 20W now, but a path has been defined for a 5X upgrade. The collector performance was reported as stable. While an NA=0.25 will likely have resolution sufficient to print ~27nm chips, getting to 22nm and beyond will require higher NA and some resolution enhancement trickery.

Thus ASML has begun work on the NXE:3300 series (figure), which will feature a 0.32 NA projection system and off-axis illumination capability. The NXE:3300B is scheduled for release early in 2012 and is targeted for 125wph throughput. However, achieving that will require a source 12X more powerful than has been demonstrated, Meiling concedes.

Direct Write Alternative

E-beam Direct Write (EbDW) lithography would appear to be a solution to the resolution limit of immersion steppers and the throughput limits of EUV, but the throughput of foreseen EbDW installations is still seen as hideously low. Laurent Pain of CEA-Leti reviewed the progress made by two European efforts: PL2 at IMS in Austria, and Mapper in the Netherlands. Three other programs exist elsewhere (figure).

Developing multi-beam EbDR tools (source: DNP)

PL2 operates at 50kV and 200X demagnification and has demonstrated 25nm half pitch. The aperture plate in today’s prototype produces 2500 individual beams, of which 90% work properly, according to Pain. Still, getting 6 wph throughput would require an installation with 76 e-beam columns (one for each exposure field) and 256,000 beams per column.

Mapper would require only 13,000 beams at 5kV, but the present prototypes operate only 110 beams…with a throughput of 0.002wph. Going to 10wph requires getting all the beams to work and raising the beam current 40X. If that could be achieved, a cluster of 10 Mappers would use less floor-space than an EUV tool and yield 100 wph. Most likely, though, EbDW would be used first for the line-cut lithography in a spacer multiple patterning scheme since the duty factor would be low, speeding throughput for the <22m cuts.

Mask making gets some attention

The mask making industry stands to benefit from developments in EbDR, according to Naoya Hayashi of DNP, since a workable wafer writing tool can be modified to write 4X masks with little difficulty. However, mask writing is no longer the cost driver or throughput gate for mask-making. Rather, inspection has taken over as the time-sink and largest expense.

Hayashi predicted that optical lithography (with very complex patterns) will likely continue to dominate for logic chip production, but other technologies like EUVL and imprint will pose different and unique challenges for mask makers if they are adopted by some industry segment. Developing the proper tool sets and processes in time will be a challenge for mask makers if there is no industry consensus. Hayashi suggested that device manufacturers and tool vendors should include mask makers in collaborations to find workable next-generation patterning solutions.

Imprint pressing on

The only pattern transfer technology that will avoid design restrictions at 11nm is imprint, according to Ben Eynon of Molecular Imprints Inc., who also predicted that NIL’s cost of ownership will be independent of resolution! MII is overcoming the limitations of its J-FIL technology and Eynon expects to see memory production with it ramp in 2012 or 2013. Defectivity is now <1/cm² in a clean-room environment, according to Eynon, and mix-and-match overlay <12nm has been achieved using template squeezing with force sensor feedback.

NIL infrastructure issues were being addressed: E-beam inspection and repair tools for the 1X master templates exist as does a capable cleaning tool. Master masks can be written slowly today at 14nm resolution with a 100kVGaussian E-beam tool, but a faster vector-scan will do 22nm. The master masks are being replicated with <20nm half pitch in MII’s TR1100 template production system. With replication, the cost of production with imprint is ¼ that of immersion double patterning and ½ the projected cost of EUV, according to Eynon. The first MII 5XX series pre-production lithography system was shipped in July.

In 2005, Ken Rygler (then the chief marketing officer of MII) bet Brian Grenon that 193nm exposure would be used for 22nm node production, with Grenon betting that something else would be needed, possibly imprint. The time is coming to find out who was right. That the issue is not already decided is a testament to the cleverness of the optical lithography community and the difficulty of every post optical alternative.—M.D.L.

Steady but undramatic progress was the theme of lithography presentations at SEMICON/West this year, not that anything more had been expected. In fact, most of the main lithography companies had decided to give the show a miss this year. TEL was the one company that had a full-scale booth, and there was a process to sell: pitch quartering! According to Masayuki Tomoyasu, chief engineer of overseas process development, TEL has a suite of equipment to fabricate 11nm half-pitch (HP) patterns in a cost effective way. Doing 22nm, the next step in Moore’s Law, would only take half the effort. Improved double-patterning results were also revealed by IMEC/ASML and by Nikon.

TEL Telindy Plus ALD tool (source: TEL)

TEL’s resist core transfer process is a variation on self-aligned sidewall double patterning, where a “core” is fabricated by standard 193nm immersion lithography, trimmed and etched, then gets coated with a sidewall material (which becomes the circuit pattern) and is finally removed. However, the TEL sidewall material is ALD SiO₂, deposited at low temperature on the resist itself, before any etching into a transfer layer.

So, after a wafer with a 40nm half-pitch resist pattern comes out of a coat-develop track, the resist and BARC (and maybe a sacrificial layer) are trimmed to 20nm CD in a TEL Tactras Vigus etcher and then conformally coated with SiO₂ at low temperature in a TEL Telindy Plus ALD system (figure). The Tactras Vigus then performs an etch-back on the SiO₂ film to open the core, etches and strips out the resist/BARC, and transfers the sidewall pattern into the hard-mask. A post-etch clean in an asher completes the process, leaving a 20nm HP grating. According to Tomoyasu, TEL showed SEMs of its own internal 300mm wafer results, not those of a customer.

To get to 11nm, the process begins at 44nm HP, and uses the ALD SiO₂ flow described above—on either the photoresist or an underlying core material—to get to 22nm HP structures. Then another ALD of SiO₂ forms new sidewalls. Finally, another multistep plasma etch process opens the tops of the conformal sidewall, removes the cores and etches the second sidewall pattern into the hard-mask. A final clean leaves an 11nm HP line-space pattern on the wafer. Edge-on SEMs showed >3:1 aspect ratios with near 90 degree profiles and good regularity. Any such multi-step process needs to be validated with extensive CD metrology and statistics, but these results indicate that 11nm is no longer a fantasy…if one can pay for 3 etches and two depositions!

Designing for double-patterning

Of course, any layout has to be drawn before it is quartered. Designing layouts that can be fabricated by such “lost-core” techniques is a challenge, but no more so than any other feasible litho method below ~65nm CD. At the Advanced Lithography Symposium held July 14 at the North Hall TechXPOT, Jongwook Kye of Global Foundries described the Design-Technology Co-Optimization (DTCO) necessary for today’s circuit scaling.

According to Kye, his “transdisciplinary” optimization is not a new idea: designers have been trying to accommodate process realities since 90nm when poly went unidirectional. Interdisciplinary communication has just produced more restrictions. At 65nm the active layer became unidirectional, and at 45nm the contact landing pads went away and poly CD became uniform. Double patterning first appeared at 32nm and now we are looking at 22nm. Interdisciplinary collaboration has become essential because the litho process choice and the decomposition for double patterning will become chip- and layer- dependent, with no single optimum method.

Don’t forget old fashioned immersion

DP budget and actual results achieved with a Nikon NSR 620D immersion stepper. (source: Nikon Precision)

At the Sokudo Litho Breakfast (ably blogged about by Toppan Photomask’s chief technology officer Franklin Kalk), Steve Renwick of Nikon predicted that process development for EUV high volume manufacturing would be delayed until 2015 due to infrastructure issues, and thus the semiconductor industry will need a bridge technology. That technology would have to leverage today’s 193nm immersion exposure tools with double patterning flows.

Source mask-optimization (SMO) with single exposure can give better process windows, but not sub-80nm pitch resolution. So, to get to 32nm HP and beyond, one needs control of CD and image placement. Renwick claimed that the Nikon NSR-620D has met the requirements for 32nm HP (figure) and also demonstrated 20nm HP lines and spaces.

IMEC, the Belgian R&D consortium, separately announced the double patterning results obtained with an ASML XT:1900i immersion stepper equipped with a FlexRay freeform illuminator (figure). Optimized freeform illumination approaches the limits of immersion lithography in geometries where traditional illumination modes cannot. The FlexRay uses a programmable array of thousands of individually adjustable micro-mirrors to create any pupil shape in a matter of minutes (see BetaSights’ exclusive prior coverage of ASML’s “Holistic Lithography”).

Comparison of ASML illumination sources for double patterning of a contact layer along with the images produced, and a table comparing exposure latitude (EL), depth of focus (DOF) and mask error enhancement factor (MEEF). The final hard-mask pattern is at right. (source: IMEC)

The demonstration announced was the contact and metal layer for a 22nm node SRAM of 0.078µm² bit cell area done by LELE double patterning into a hard mask, with the application of simultaneous source - mask optimization (SMO) and FlexRay illumination. The asymmetric X Y positions of the freeform poles cannot be mimicked in a standard source, but would require a custom diffractive optical element likely requiring weeks to deliver.

Stay tuned for a future blog posting about recent EUV, EbDW, and NIL developments.—M.D.L.

After at least a year of being in denial, Applied Materials (AMAT) finally acknowledged some of the reality that there is no market for 6% efficient photovoltaic (PV) fab lines, and killed the “SunFab” that has been sold to unfortunates over the last few years. With no new customers expected, and old customers going bankrupt or having to retool lines to stay running, these thin-film amorphous-silicon (TF a-Si) on glass turnkey production lines are clearly not capable of keeping up with 20% efficient crystalline-silicon (c-Si) and 10% efficient TF technologies. However, the company CEO refuses to acknowledge any mistakes, says they’ll fill the backlog, and claims that, “competitive pressures from crystalline silicon…did not allow the market to take off.” First Solar shipped ~1GW of ~10% efficient TF PV in 2009. The market took off, just not with SunFabs.

AMAT chairman of the board of directors, president, and CEO Mike Splinter further asserted that, “SunFab is a remarkable product. Unlike anything we have done before, it is an example of the kind of revolutionary innovation that Applied Materials is capable of producing. In just a few years we developed a turnkey solution, successfully executed our technology roadmap, achieving greater than 10% stabilized module efficiency and silicon uniformity across the 5.7 square-meter substrate.”

The above quote—part of Splinter’s online video non-acceptance of responsibility—is an amazing example of corporate double-speak, in that each sentence is factually correct while evading key facts. In recent months the world has seen the CEOs of BP, Toyota, and Apple issue various official statements to deal with problems; evasive corporate positioning statements never help in the end.

Let’s examine Splinter’s evasions in some detail:

1. Quickly developed a turnkey solution – by cobbling together old in-house FPD tools with pricey technology acquisitions the company did offer a turnkey line (figure)…where just the tool depreciation costs alone could be estimated to add $0.60/W to manufacturing cost (see below).

2. Successfully executed the technology roadmap – while utterly failing to execute on a business roadmap that could provide competitive products to the market.

3. Achieved >10% stabilized module efficiency – sure, downhill with the wind on a good day in the lab at extra cost for dual- and tri-layer materials stacks…while routine cost-effective fab results remained at 6% for a single layer.

AMAT will, of course, continue to try to sell over-priced support services to the unfortunates who bought SunFabs, so some of the people who had been working in the PV division will be moved over to the “Repairs & Spares” division. The company’s Xi’an, China PV R&D center will cease working on TF technology and will focus on mc-Si and c-Si wafers instead. The c-Si PV tools sold by AMAT—essentially all of which were acquired over the last four years—continue to do well in the market. Still, the company will likely lose hundreds of employees and will write-off ~$400M. Mark Pinto will remain in charge of PV products as executive vice president and general manager of the Energy and Environmental Solution (ESS) group, while also remaining as CTO of AMAT Corp.

In the video Splinter said, “Innovation is the heart of our company. We’ll take the lessons from SunFab and use them to make us stronger.”

What lessons might we learn from SunFab?

1. If you supply technology, don’t bet the company against innovation. When AMAT launched SunFab it was a bet that innovation in thin-film PV would not succeed. Choosing 6% efficient and mature a-Si technology in 2006 was a bet against less-mature CdTe and CIGS thin-film technologies (had First Solar failed to develop $1/Wp with 10% efficient CdTe then things might be different for a-Si in 2010).

2. If you buy technology, don’t bet the company against innovation. After betting the company on a SunFab line, Sunfilm AG in Grossroehrsdorf, Germany filed for bankruptcy protection on March 26 of this year. After buying a standard (40MW/year @ 6% efficiency) SunFab, Moser Baer in Greater Noida, India (also with 80MW/year c-Si cell/module fab capacity) had to idle the TF line for much of 2009 while working to customize it such that it could deliver ~7% efficiency. Signet Solar in Dresden, German used over a year of depreciation of a SunFab line to deliver a grand total of 10MW to the field, while it also did it’s own upgrade to ~7% efficiency.

3. Do the math. A basic 40MW/year capacity SunFab line was priced at ~US$120M; assuming 5-year linear depreciation, this results in $0.60/W just to pay for the cost of equipment depreciation! Considering the rule-of-thumb that the module cost is ~60% of the total installation cost, and that total cost scales with the area to be installed, and that First Solar’s ~10% efficient modules set $1/W price-points for TF, it seems that you would have to sell 6% efficient a-Si panels for $0.60/W to try to complete…the same price you pay just to own the tooling! Maybe a vertically integrated company building solar farms like T-Solar can afford to run a SunFab line at a loss, but even they might see reduced farm costs with buying mc-Si or c-Si modules on the open market.

(Source: NREL, 2007)

Research efficiencies (figure) are not the same as fab efficiencies, but the more mature the technology the closer fab efficiencies are to their practical limits. When SunFab was conceived, the maximum lab result was 12% for a-Si TF PV, and having already been run in fabs for decades was known to result in ~6% efficiency in production. In contrast, while both CdTe and CIGS had been explored in labs for decades with champion results reaching to 16-18%, fab processes were still relatively immature and could thus be expected to improve significantly over time from ~6%.

The reality of the PV module market is that CdTe and CIGS TF technology suppliers continue to innovate in their fabs, with First Solar leading the way down the $/W learning curve. Fabs still trying to run a-Si at 6-7% efficiency face a serious gap compared to ~10%, and stacking a multi-crystalline (mc-Si) TF over the a-Si to create a more expensive “tandem junction” really only provides 8-9%.

In the analysts’ question-and-answer sessions today, AMAT executives continue to assert that tandem junction TF will win in the market when a-Si fails, so that the company will sell new mc-Si CVD tools to old a-Si SunFab lines eventually. However, if the cost/benefit argument is valid for a-Si/mc-Si TF then why wouldn’t all customers opt for this today?

The only reason AMAT has a story to tell in PV today is because of the acquired portfolio of c-Si OEMs. With SunFab, Splinter effectively bet the company against thin-film innovation. How sad and ironic for a company that was built on thin-film technology innovation (for IC fabs).

There are thousands of hardworking engineers and technicians who’ve lost years of their lives by mistakenly working on SunFab, both within AMAT and at customer sites. Investors into companies buying SunFab lines stand to lose hundred of millions of dollars. The entire PV industry loses credibility when AMAT’s SunFab is added into high profile technology blunders like Nanosolar. What have we learned again? -E.K.

Two of the biggest original equipment manufacturers (OEM) supplying semiconductor fabs have released new etch chambers that are tuned for the selective removal of mere monolayers. Applied Materials just announced a new “Mesa” field-retrofittable upgrade to it’s “AdvantEdge” ICP etch chamber, targeting several challenging new applications. Tokyo Electron provided an update to applications plans for the Radial Line Slot Antenna (RLSA) chamber first announced in March of this year. Both tools have reportedly passed

SEMI CEO Stan Myers opens Intersolar 2010

beta-site tests, as this editor mentioned in his invited talk at the NCCAVS Plasma Applications Group meeting, held July 15 this year on the floor of SEMICON/West-Intersolar (figure).

Single-wafer etch chambers have historically been designed for maximum etch rates to deal with microns of material, starting from the first etcher released in 1979 by Tegal (still supplying tools {Thanks to Tegal vice president Paul Werbaneth for the invitation to present at the NCCAVS-PAG}).

From the 1981 release of the Lam AutoEtch 480—featuring atmospheric loadlocks and fully automated recipe control—to today’s tools handling 45nm CDs, maximum etch rate has always led to greater throughput and thus to better Cost-of-Ownership (CoO). However, for 45nm node and below ICs, Dennard Scaling in support of Moore’s Law has led us to device structures where critical materials are now measured in terms of monolayers. The result is an opening in the market for process chambers that are specifically designed to etch as little as a single layer of atoms across 300mm wafers.

However, we are specifically not considering the use of true atomic-layer etch (ALE)—conceptually similar to atomic-layer deposition (ALD) where reactants first adsorb then react and byproducts somehow finally sublimate—for chip manufacturing yet. Nor are we considering the use of neutral ion-beams which can remove atomic layers but generally lack selectivity to underlying materials. At present, it seems that we only need to extend legacy etch chambers with new sources and recipes to be able to meet current needs. How needy are we these days?

Perhaps the most challenging etch need today is for high-k metal-gate (HKMG) transistors used in 45nm and below CMOS ICs, where work-function altering oxides of aluminum and lanthanum are less than 1 nm thick. Since the gate is the heart of the transistor, any variation in etch profile across the wafer directly results in final device variability, and so as a rule of thumb we must control the etch to 10% of thickness…less than a single atom.

Originally developed for satellite broadcasting, RLSA has been explored as a plasma source by Tokyo Electron for many years (figure). Work at the Tokyo Electron Technology Development Institute in Hyogo, Japan has been led by vice president and general manager Tosh Nozawa. In an exclusive interview with BetaSights, Nozawa-san explained that the 2.45 GHz RLSA source demonstrates the unique ability to provide uniform etching across an extraordinarily wide pressure range: from 5 mT up to 5T.

(US Patent App. Pub. No. US 2008/0142159 A1)

RLSA etching provides relatively high densities of radicals decoupled from the electron temperature (figure). The wafer is not completely “downstream” from the plasma, so anisotropy can be maintained with bias. However, the electron temperature can be as low as 1 eV at the wafer surface, and TEL reports minimal charging damage on sensitive test structures compared to legacy sources.

Applied Materials has found a way to extend a legacy inductively-coupled plasma (ICP) source with two complementary techniques: additional source-coil complexity, and an innovative way to synchronize pulses to both the source and bias powers. Standard ICP source coils have been split in two, which allows for cross-chamber tuning of the electric field (figure). The result is better control of etch rate over the 300mm wafer surface, and the ability to fine tune within-wafer uniformity.

More innovative is the new source-bias sync (figure) that provides superior within-die uniformity. When power is off during the cycle, there are several significant local uniformity benefits:

• charging on the etch mask has time to dissipate,
• byproducts inside recesses have time to exit, and
• reactants have time to refresh surfaces inside recesses.

Also, the duty cycle can be adjusted to seriously slow down the process to handle monolayers. “For example, the etch rate can be tuned down to one Angstrom/minute using chlorine plasma,” claimed Thornsten Lill, Applied Materials’ vice president of etch technology development, in an exclusive interview with BetaSights. Compared to a continuous-wave plasma that over-etches 4nm, the synchronous pulsing over-etches <1nm.

Applied Materials reports that the combination of the split ICP source with source-bias-sync significantly improves the depth uniformity when there is no etch-stop, such as in shallow-trench isolation (STI) and buried word-line (bWL) etches into silicon. The company claims 1% silicon etch-depth can be maintained across 300mm wafers, and <1 nm (3 sigma) CD for lines/spaces. Where the use of a continuous wave source would result in measurable non-uniformity in etching trenches, the pulsing source reduces the non-uniformity by 2/3.

TEL has provided the forward-looking-statement that 20 chambers are expected to be sold in the first year, for applications in both transistor and interconnect formation. Applied Materials has provided the backward-looking statement that it has shipped >60 chambers over the last 6 months to etch both metals and silicon, and that the hardware changes can be field-retrofitted in a single production shift. Based purely on end-user demand, it is likely that other OEMs will release new or significantly upgraded plasma etch chambers, and the market for soft plasma etchers will be very dynamic for the next few years. “The more selectivity you have in the etch the more flexibility you have in the overall integration,” said Uday Mitra, Applied Materials’ vice president and chief technical officer of etch, in an exclusive interview with BetaSights. For process development and integration, these new etch capabilities are very welcome additions to the metaphorical tool-box. –E.K.

With the world now manufacturing nanoscale ICs and MEMS, new devices require the formation of thin-film coatings from exotic material precursors. Atomic-layer depostion (ALD) as an extension of chemical vapor deposition (CVD) technology can be used to form both dielectric barriers and metal connections. With a tool designed to deposit almost any thin film, French OEM Altatech Semiconductor S.A., has recently received orders for ALD/CVD systems that will be used for the R&D of 3D and high-mobility ICs.

In May of this year, the Fraunhofer Research Institution for Electronic Nano Systems (Fraunhofer ENAS) in Chemnitz, Germany, ordered an AltaCVD system (figure) from Altatech to deposit advanced silicon stressor materials on 200mm wafers. Silicon stressor materials are used to increase the channel mobility of transistors, enabling higher processing speeds.

Fraunhofer ENAS is scheduled to install the new AltaCVD system in its back-end-of-line (BEOL) cleanroom facility in Chemnitz during the second quarter. A previously installed system is being used to deposit diffusion barrier and copper layers for advanced copper damascene interconnects and through-silicon-via (TSV) features.

“After evaluating Altatech’s innovative technology and its AltaCVD equipment, we have ordered a system for our lab, where we’re developing nanometric thin films to advance the state of semiconductor processing. The use of liquid-phase precursor injection and evaporation is a key enabling technology for this work,” said Prof. Stefan E. Schulz, head of back-end-of-line operations at Fraunhofer ENAS.

Altatech also won an order by Fraunhofer IZM’s new All Silicon System Integration Dresden (ASSID) group for a 300mm AltaCVD system. Just opened on 31 May 2010, the ASSID is specially designed for projects in 3D wafer-level system integration (200/300 mm) and prototype development for manufacturing partners in industry. As part of the Fraunhofer IZM Institute, which specializes in transferring IC advanced packaging and system integration research results to industry, ASSID is integrated into a technology network of applied research institutes and universities.

The equipment is scheduled to go online in the third quarter of this year at ASSID. The site’s Class 1,000 cleanroom is equipped with a complete 300mm wafer fabrication line for TSV formation and post-processing on both the frontside and backside of wafers, wafer thinning, 3D device stacking, and package assembly and testing. ASSID will use the AltaCVD system to create through silicon vias (TSV), processing both standard and thin silicon wafers. The low-temperature AltaCVD tool will deposit stacks of film layers and ultrathin, conformal isolation layers inside deep vias and trenches with aspect ratios as high as 40:1.

In addition to handling either 200 mm or 300 mm wafers, AltaCVD’s flexible architecture allows it to be used in volume production for plasma-enhanced deposition (PECVD) of dielectric materials, stacks and metal films as well as in R&D for metal-organic processing (MOCVD) in back-end-of-line (BEOL) applications such as creating direct-platable barriers.

Altatech Semiconductor’s AltaCVD platform uses direct injection of liquid precursors and an advanced flash-vaporization system in processing wafers up to 300 mm. The modular system can accommodate a wide range of vaporization and deposition temperatures, enabling users to select the optimal process windows for their specific applications, which can include deposition of advanced materials for high-k gate dielectrics, metal gate electrodes, capacitors and 3D integration. For thermal CVD or RF-enhanced deposition steps, a low-frequency plasma enables tuning of the thin film’s mechanical, electrical and optical properties.

“Through our partnerships with Fraunhofer ENAS and other leading research centers, we are continuing to develop liquid-precursor deposition processes for high-k/metal gates, through-silicon-vias, memory and capacitor applications,” said Jean-Luc Delcarri, president of Altatech Semiconductor. “We’re also working with IDMs and foundries to bring liquid-precursor deposition to their high-volume 300 mm fabs. And we’ve begun applying our CVD technology to create advanced thin films for solar cells, high-brightness LEDs and other microelectronics markets.”

Key features of Altatech’s low-pressure injection (LPI) vaporizer (figure):

• Improved atomization, due to carrier gas “blasting” the flow into claimed 5-40µm droplet diameter range with maximum population at 10µm (compared to 6 to 60µm with max population at 22µm for high-pressure direct injection),

• Longer droplet residence time inside the vaporizer due to low liquid pressure (2 to 5 bar), and

• Sequential or co-injection from 2-4 injection heads provides for binary or higher order alloy deposition, and the ability to form nano-laminates in a single-chamber.

With the above capabilities in the source injector, the company claims that the system can work with any of the following liquid precursors:

• TEOS,

• n-octadecyl trimethoxysilane,

• glycidil methacrylate,

• n-hexadecane,

• III/V precursors (TMGa, TMAl, Cp2Mg, etc.), and

• Proprietary organometallics (Cupraselect™ for Cu, Chorus™ for Ru, etc.).

Diluted solid precursors such as ß-diketonates, Alkoxides, and proprietary molecules can also be vaporized by the system.

“Through our partnerships with Fraunhofer ENAS and other leading research centers, we are continuing to develop liquid-precursor deposition processes for high-k/metal gates, through-silicon-vias, memory and capacitor applications,” said Jean-Luc Delcarri, president of Altatech Semiconductor. “We’re also working with IDMs and foundries to bring liquid-precursor deposition to their high-volume 300 mm fabs. And we’ve begun applying our CVD technology to create advanced thin films for solar cells, high-brightness LEDs and other microelectronics markets.”

No deposited film exists independently, and the smaller the device structure the tighter the integration required. Films that play an active role in the device function—such as high-k metal gates (HKMG) for 32nm node CMOS ICs—must be carefully integrated with various physical and electrical barrier layers. High-volume manufacturing (HVM) necessarily changes as little as possible, and so any new material must always fit into old flows, and any new tool must be proven as reliable.

Liquid-precursors have always been challenging to handle in CVD systems: bubblers tend to lack precision, and vaporizers generally lack reliability. Vaporizers have been used for decades, yet nozzles still get clogged, and interior walls still build-up particle contamination. Encouragingly, in an email exchange with BetaSights, Altatech claimed that it’s low-pressure injector design allows for 6 months of “production mode” use between preventative maintenance (PM) cleanings of the vaporizer.–E.K.

While most of the IC manfacturing world has embraced the fabless/foundry split between design and manufacturing, Intel has remained staunchly vertically integrated and continues to reap the rewards. At the recent 2010 International Interconnect Technology Conference (IITC) in Burlingame, California, researchers from Intel confirmed that the design constraint of a fixed spacing between interconnect lines allows for the use of “air-gaps” in manufacturing to increase circuit speeds. While this approach has been considered for over 20 years, today no other company has all of it’s logic chip designs converted from anything-goes 2D to strict 1D layouts. Consequently, no other IC company can easily use this low-cost manufacturing trick today, even though EDA startup Tela Innovations has been selling gridded-design-rule (GDR) IP for a while now.

CVD can be easily tuned to initially coat sidewalls (top), then pinch-off (middle), and finally form a closed pore (bottom) during one step.

With shrinking IC sizes, the dielectric insulation between metal interconnects has become one of the major limits on increasing circuit speed, so the last 15 years has seen relentless pursuit of ever lower capacitance (“k” value) dielectric materials to replace SiO2 glass (k~4.0). Sadly, there are many devilish details of materials integration into nanometer-era ICs, and one by one the dozens of possible new low-k materials failed to meet specifications: too leaky, too soft, too unstable, and too expensive. The history of this debacle can be read in the wishful thinking specification for low-k dielectrics found in successive versions of the International Technology Roadmap for Semiconductors (ITRS) from 1998 to 2008. In 2010, with a few very limited exceptions, the only low-k dielectric used in commercial fabs is CVD SiOC(H) with k~3.0.

In fact, CVD SiOC(H) is such a good dielectric that nearly all attempts to reach k<2.5 now use this material as part of the final structure. Empirically, it has been found that nanometer-scale pores can be created in SiOC(H), and such porous low-k (PLK) films can get to ~10% porosity for a k~2.7 without too many problems. However, aiming for lower k-value generally results in connected pores that make soft and leaky and unstable films, and the work-arounds add expense and uncertainty. Still, as shown at IITC, most fabs are still pursuing work-arounds to strengthen, stabilize, and cap PLK films. In contast, Intel has chosen to add a single central pore to SiOC(H) so get to lower k (see figure).

To be clear, there is no “air” in what is not really a “gap” in an air-gap; it’s more like vacuum inside of elongated holes. Intel has developed an air-gap process that uses no new materials, and requires only dry 193nm lithography for one additional masking step:

1. Standard Cu dual-damascene interconnect formation,

2. Mask using 2x minimum CD (allowing for dry 193nm),

3. Etch out dielectric (preserving via landings and wide areas),

4. CVD of a conformal dielectric liner, and

5. CVD to partially fill and “pinch-off” the top openings of the gaps.

Note that, despite repeated questions from the audience, the Intel presenter refused to say which materials are used for the two final dielectric, nor the final effective k-value of the structure.

32nm node IC interconnect structures showing air-gaps (source: Intel)

However, the company disclosed that for the tightest-pitch interconnect layer (56nm for both lines and spaces) on 32nm node test chips (see figure), a >20% reduction in the effective capacitance was achieved with air-gaps. Moreover, the company claims that 22nm node test chips show ~28% capacitance reduction compared to full SiOC(H). While the specific dielectrics used were not disclosed, from known films we can guess likely scenarios. The pinch-off dielectric is almost certainly SiOC(H), since any other stable material would have k>3 and would increase the effective k too much. The conformal CVD film could be SiOC(H), or SiO2, or even SiC since the k value of a liner would add relatively little to the final effective k.

The lithographic masking step is needed for two reliability reasons. First, by excluding air-gap formation in areas near next-layer vias, alignment between layers can be more easily done. Second, wide spaces are excluded where the final non-conformal CVD step wouldn’t automatically pinch-off to close the gaps; leaving full SiOC(H) in wider spaces also helps with mechanical strength. The next layer is patterned with a conventional daul-damascene flow, with the option to add air-gaps.

Dry 193nm litho used to mask off areas with no air-gaps (source: Intel)

With the masking step to improve reliability and lifetime (see figure), and with etch and deposition optimization, Intel claims that air-gap pilot manufacturing yield for 32nm SRAM tightest-pitch layers is similar to the process-of-record (POR). The company tested dielectric breakdown and thermo-mechanical packaging issues with various air-gap integration flows, and found that the proper combination of barrier layers allowed for equivalent results to the POR. The quality of the interface between the conformal CVD dielectric and the metal is important. Also, the quality of the metal barrier must be good to eliminate fast diffusion paths that could induce unacceptable levels of electromigration.

Perhaps the most significant claim of this new interconnect process flow is that no new failure modes were reportedly observed. In contrast, PLK process flows to get to >10% porosity use new materials and new process steps that almost always combine to produce new ways for the integration to fail, which is another reason that PLK dielectrics have so far failed to replace SiOC(H).

Remembering that Intel is the company that Andy Grove built, and that Grove wrote the book entitled “Only the paranoid survive,” it remains reasonable to consider mildly paranoid theories about the company’s motives. In particular, history has shown that next generation technology announcments can sometimes be deliberate mis-directions: publishing detailed maps that just happen to omit known dead-ends. Intel has not said it will ever use air-gaps in production. All the company has said is that it could use air-gaps in production with good results. Since it is the only known IC company with 1D logic designs ready to go, it could happen for 22nm node manufacturing.

Thorough coverage of IITC this year has been provided by industry expert and Techcet analyst Mike Fury, who attended the full conference including the short-course. Fury’s wit often equals his wisdom, even if he has pony-tail envy. –E.K.

HP Labs in Palo Alto has been leading the development of the “memristor,” and researchers there have finally discovered the underlying mechanism for the formation of devices that can function as memory cells, logic circuits, and potentially even real artificial intelligence (AI)! Disclosing these results in his plenary speech to the attendees at the Nanocontacts and Nanointerconnects Workshop at the Spring 2010 Materials Research Society meeting on April 5th in San Francisco, HP Labs group leader Stan Williams (figure) explained how to make memristors without use of the hitherto-uncontrollable “electroforming” step.

Stan Williams (source: HP)

At the risk of oversimplifying, a memristor can be thought of as a complex oxide sandwiched between two metal contacts, where the electrical resistance of the oxide changes due to current-flux induced ion drift that forms conductive filaments. Memristors were famously predicted in theory in 1971 by Leon Chua of U.C. Berkeley (Ref: IEEE Trans Circuit Theory 18, 507-519; 1971), yet theory provided no clues for practice, and it was only in 2008 that the Williams Group proved the function in oxides of titanium. “Leon Chua is the Albert Einstein of circuit theory,” declared Williams.

One of the biggest problems with HVM of memristor circuits had been that PVD of pure “rutile” (TiO2) titania results in simple resistors. Before these simple static resistors can become dynamic memristors, they have to be “electroformed” using a strong voltage-current applied for a minimum time. Electroforming was known to induce movements of ions and defects in the oxide, but we did not really know what final structure was created, and so could not begin to control the process so as to be able to integrate it into a complete device HVM flow.

“We spent ten years messing around making all the wrong measurements and coming to all the wrong conclusions before we discovered that these things are memristors, and we had to do time-dependent measurements,” explained Williams.

Williams’ Group at HP finally went through great expense and effort, networking with U.S. government labs for access to nanoscale materials characterization tools, to dissect memristors pre- and post-electroforming to determine what was happening at the atomic level. They found that electroforming was reducing the rutile TiO2 to a single-crystal of “magneli phase” Ti4O7 under each contact. For large area contacts, the Ti4O7 always appeared like a ~100nm diameter nanoscale plug relatively independent of the contact area, since essentially all the current flowed through this one plug during electroforming.

At geometries near optimal for memristor function, a 1-2nm thin TiO2 layer remained as a tunnel barrier. The width of the tunnel barrier then changed by ~0.5nm by the movement of ions within the oxide during memristor function. The switching mechanism for the memristor is thus field-induced drift of positively charged O+ vacancies in TiO2 that controls the resistance of the film. The Ti4O7 functions as a source/sink of O+ vacancies to diffuse into and out of the TiO2. “This can be thought of as a condensed phase of vacancies in TiO2,” according to Williams.

With this new understanding, Williams’ Group was able to conceive of forming the final device structure without having to electroform. Sourcing a new Ti4O7 PVD target, they now sputter 25-30nm of Ti4O7 followed by 1-2nm of standard TiO2 between ~15nm thick Pt electrodes (figure). To avoid oxidation of the bottom Pt electrode, they discovered that a few nm of Ti deposited below the electrode provides sufficient Ti to diffuse through the Pt and pin any vacancies at the Pt/Ti4O7 interface.

Other oxides sandwiched between other metals can also become memristors. Tradeoffs in materials selection involve switching speeds, device lifetimes, and manufacturing costs. While HP has led the world in pursuing memristor technology using the Pt/TixOy/Pt stack, there has been a rush of global R&D in both academia and industry to explore other materials systems. Indeed, there were dozens of papers presented at the Spring MRS Meeting on devices based on ionic transport in oxides to controllably change the resistance, however all of the presentations seen by this editor included mention of electroforming as part of the manufacturing flow. While additional materials engineering is needed to create high-yielding memristor arrays in high-volume manufacturing (HVM), it looks like everyone now has to agree upon two facts:

•    from a HVM perspective, non-electroforming is the only way to go, and
•    from a design perspective, memristors are intrinsically dynamic devices.

Memristors for ReRAM
HP Labs has been working on the smallest possible memory elements using cross-bar architectures. At the types of fields you can put on a nanoscale device you have to be concerned with the potential for damage at contacts. Argonne National Lab is testing some of the HP Labs’ newest 20nm line/space crossbar structures, but it is not easy to push the limits of the nanoscale manufacturing. For example, impedance spectroscopy is not so useful, because in non-linear devices the whole concept of impedance is not even valid.

Despite the difficulty to dynamically measure memristors, now that they are not-so-difficult to make we can use static properties to make memory arrays. With the ability to switch the resistance quickly between relatively high and low static states, we can make random-access memory (RAM) cross-bar array circuits with densities that beat Flash for equal minimum critical dimension on chip.

The main limitation now holding fabs back from making high-yielding ReRAMs is probably the Pt electrodes. So far, noble metal contacts seem to be essential to prevent contact oxidation and parasitic resistances, and noble metal patterning generally requires “lift-off” integration which can be problematic in geometries smaller than several microns. Still, lift-off is easily controlled for larger geometries, and the use of sidewall spacers and sacrificial masking layers may allow for high-yielding extendibility to <20nm and smaller devices.

Memristors for logic
There is an ongoing need to be able to create ever faster devices that can “flop” as elements of logic circuits. As Ghavam Shahidi of IBM Research in Yorktown Heights, NY presented at the “Device Architecture: Ultimate Planar CMOS Limit and Sub-32nm Device Options” short course at IEDM 2009, the world now has the ability to create 12.64 TeraFLOP ICs, with ExaFLOP ICs imagined by the year 2020. Extrapolating today’s state-of-the-art planar CMOS IC parameters out to ExaFLOP requirements, the power consumption would be 100s of MW to a few GW (for reference, a nuclear reactor typically produces ~1GW). Massive memristor arrays could theoretically provide high-speed logic functions with dramatically reduced power consumption compared to CMOS.

Since the memristor is a dynamical device, it changes with time, and two equations are needed to describe the device. All measurements must be made explicitly over time; not on a curve tracer, but by creating a state and then watching how the state changes over time. For example, starting with a nominal 1ms electrical pulse, and then applying a smaller bias voltage.

With only one variable changing—the width of the tunnel gap from 1.2 to 1.8nm—HP’s researchers found that they can fit the barrier heights and all other parameters to classic I/V curves using the Simmons Equation. For the width of the tunnel barrier varying over this range, the potential needed to switch a memristor ON varied from -1.25 to –1.4V, and the potential needed to switch a memristor OFF varied from +3.0 to +5.5V.

HP Labs’ has already reported on relay logic (without gain), information-packet and redundant-wire concepts to allow for 100% information transfer through 90% functional connections, and configurable interconnect layers for ASIC/FPGA hybrid functionality. Adding all of these technologies together results in unprecedented capabilities to create new logic circuits with uniquely valuable capabilities.

Memristors for AI
Perhaps the most elusive value in logic ICs has been anything associated with artificial intelligence (AI). Despite decades of theory and grandstanding by proponents such as Marvin Minsky, AI in practice has seemingly failed to create even the simplest circuit that can learn. Perhaps binary logic is inherently inadequate for AI, but analog logic based on memristors could work. “Since our brains are made of memristors, the flood gate is now open for commercialization of computers that would compute like human brains, which is totally different from the von Neumann architecture underpinning all digital computers,” predicted Chua.

UofM researchers work on memristor synapses (source: Nano Letters, DOI:10.1021/nl904092h)

We now know that neuro-plasticity describes the ability of human neuronal networks to selectively form stronger or weaker connections as examples of adaptive learning. Neurons are triggered by ionic transport across the synaptic cleft—with nominal spacing <10nm (figure)—and since a neuron’s function varies with an “action potential” that creates non-linear dependencies, a memristor may be the closest solid-state electronic device we have found that mimics the function of a neuron.

Perhaps dense arrays of memristors could be somehow wired together to learn from inputs so as to create artificial intelligence (AI). Researchers in the Lu Group at the University of Michigan have already shown that, “a hybrid system composed of CMOS neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity.” Maybe a massive memristor array will eventually be part of a system that will pass the Turing Test, and we’ll be one step closer to meeting Marvin the Paranoid Android. –E.K.

The 2010 SPIE Advanced Lithography conference is where we first get glimpses of the future of nano-scale patterning technology for manufacturing. Sometimes, many fuzzy blobs come into focus as a picture in a single moment, and Yan Borodovsky of Intel showed how to do 22nm node litho the day before SPIE officially started. At both Nikon Precision Corp.’s afternoon event, and again at KLA-Tencor’s event in the evening, he showed the tremendous advantages of forcing IC designs into stacks of one-dimensional (1D) patterns.

With optical lithography limited to 193nm illumination and 1.35 N.A. lens-stacks, there are now serious scaling limits in high-volume manufacturing (HVM) of ICs. No matter what source-mask optimization (SMO) tricks are used, the limit to the pitch that can be patterned in a single exposure using a resist with a monotonic relation between dose and development rate is 72nm. Extreme ultra-violet (EUV, at 13.5nm wavelength) lithography is not ready, electron-beam direct-write (EBDW) is too slow, and directed self-assembly (DSA) of molecules remains unproven for IC patterning.

IC standard cell designed with one-dimensional layouts (source: Tela Innovations)

Consequently, it has become more and more expensive to make 2D patterns, and at some point we have to accept the design constraint of strict 1D layouts for logic. While IBM/GlobalFoundries claims to want to keep 2D layouts for logic, Intel began transforming its design intellectual property (IP) from 2D patterns into essentially 1D patterns years ago, and is currently in HVM using lines with a second “cut” mask for logic chips. Sidewall spacer pitch doubling is used for HVM Flash memory today. TSMC is working with Tela Innovations to promote the concept of highly regular layouts; Tela licenses standard cell IP (figure) as well as 2D-to-1D layout transformation services.

Chris Mack, gentleman scientist, provided a wonderful daily blog from SPIE this year, and his February 23 posting summarizes the recent clarity:

“I find it very interesting to see various players in the industry slowly getting behind this basic double-patterning strategy: Designs are restricted to essentially one-dimensional features of a single pitch on a grid. The first patterning step uses 193i with sidewall-spacer pitch doubling that can get the final pitch down to around 38 - 40 nm. A second patterning step then cuts the lines to make the final pattern. The resolution of the second patterning step determines the tip-to-tip spacing of the line patterns, but is a secondary (though important) influencer of packing density. What tool will do the cutting? Immersion with all the optical tricks? Multiple e-beams? EUV?”

To allow for routing connections in logic circuits, the transistors cannot be packed as closely as possible. Generally, compared to the line width, the space between lines is set three times greater. “It turns out that 1:3 is the sweet spot for gratings if you have a low-flare tool,” commented BetaSights’ M. David Levenson. “So long as you can keep the true pitch above 80nm or so, 193i will work for 1-D gratings with one exposure.”

One exposure forms regular dense line arrays, followed by plasma etching to “trim” the linewidths, followed by the second “cut” exposure, to form the final pattern.

For 22nm logic transistor minimum gate dimensions, the first step is to create gratings of periodic and uniform lines and spaces at 88nm pitch. Then a traditional plasma etch tool “trims” a few nanometers from the sides of the lines to form the grating structures with 22nm lines and 66nm spaces. After exposure with the second “cut” mask, the pattern is transferred to the wafer (figure). This fab flow is what allows Intel to enjoy low defect levels and high yields in HVM. Though two patterning steps are needed, the costs are minimized since each step is easier and proper design can expand the overlay tolerance.

Periodic Structures is a new startup-launched with some US government funding-that is trying to create a new exposure tool designed exclusively to form (as per the company name) periodic gratings for the first exposure in this flow. Talking with BetaSights, co-founder Rudi Hendel explained that it’s overkill to use lenses capable of 2D patterning to form gratings, and that they have proven the concept of a significantly less expensive 1D imaging system.

Even with the most efficient “mix & match” exposure tool strategy, double-patterning flows are certainly complex. Former Intel lithography expert Alexander Starikov, current operating I&I Consulting, in a private conversation with BetaSights, wisely noted that all double-patterning schemes actually require three patterning steps for metal interconnect layers! This is because the edges of regular arrays in one IP block generally have to connect with another array or bond pads and somehow non-regular patterns must be formed.

Levenson has identified and long promoted another lithography approach that is conceptually similar to line-cut double-patterning: “Vortex-blanking” double-patterning. Used to form contact patterns, a regular “Vortex Array” mask creates minimally sized dense arrays in a single exposure, to be followed with a second blanking mask to create the final sparse contact pattern for logic (figure). In this method, the phase-shift mask (PSM) structures create the finest spacings possible in a single exposure of a negative resist, and then the block-out mask exposes the ones that you don’t want to print.

Two exposures with Vortex array and blockout (“trim”) mask equalizes CDs across pitch (source: M. David Levenson)

The limit of HVM litho so far has probably been seen in research for the hard-disk-drive (HDD) industry. To get to the smallest possible patterned bit media (PBM), researchers first use EBDW to form sparse posts, followed by DSA of co-polymers to form dense arrays, followed by pattern transfer to form nano-imprint-litho (NIL) master templates with the densest possible 1D structures. Of course, there are essentially no overlay issues with HDD media.

NIL hope for 2D

Perhaps the last best-hope for 22nm 2D patterns comes from NIL. In private conversation with BetaSights, Mark Melliar-Smith of Molecular Imprints Inc. said that his company’s NIL overlay has already been reduced below 20nm in mix and match applications with a 193nm immersion stepper. Data taken at SEMATECH indicates that overlay can be improved with frequent template cleaning or overfill-insensitive alignment marks. At 22nm, Melliar-Smith predicted his company’s jet and flash imprint lithography (J-FIL) technology will have the lowest CoO - neglecting mask cost.

Mask cost and lifetimes may not be a gating factor for the adoption of NIL in HVM of ICs. DNP has already produced 14nm line-space J-FIL masks, according to Naoya Hayashi of DNP. Masks with the 22nm patterns needed for NAND flash in 2013 can now be produced using a 50KV e-beam tool. The etch depth uniformity of 1.8nm is good enough already. However, Hayashi worries that there is no inspection tool for imprint templates, forcing vendors to rely on wafer inspection. Even a new Hermes MicroVision inspection tool will take 32 hours to inspect one field. DNP expects to begin production of replica templates by imprinting the master masks in 2012. Template repair has been proven to work at 32nm, Hayashi reports. -E.K.

The upcoming Spring Materials Research Society (MRS) Meeting in San Francisco will feature a separate “Nanocontact and Nanointerconnects Workshop” to explore the biggest secret about the smallest devices: for the near-term there’s nothing better than standard metal. The workshop will address both theoretical and experimental approaches to formation, carrier transport, and reliability, and so will also explore the long-term potential for novel materials and structures.

Whether it’s a quantum dot for memory, a self-assembled molecule for a switch, or a carbon-nanotube (CNT) sensor, it needs electrical connections for power and signals. As new materials with novel composition and geometry are explored, the underlying physics of contact/interconnect formation and carrier transport needs to be re-examined.

The scheduled speakers for the all-day event are as follows:

• Stan Williams, HP Labs (plenary), Palo Alto, USA
• Paul S. Ho, University of Texas, Austin, USA
• Suzanne Mohney, Penn State University, USA
• Francois Leonard, Sandia National Labs, USA
• Juan Jose Palacios, Universidad de Alicante, Spain
• Richard Martel, University of Montreal, Canada
• Jon Pelz, Ohio State University, USA
• Ingann Chen, National Cheng Kung University, Taiwan
• Hanno H. Weitering, University of Tennessee/Oakridge National Lab, USA

In the real world of high volume manufacturing (HVM) of nanoscale devices, the performance is typically gated by the interconnect. The speed of the switch is now generally faster than the time needed to get electrons to flow down the wire to the switch. The resolution of the sensor array is now limited by the shadows from the wires. Converting a signal between electrons and photons—using detectors and laser diodes—adds unacceptable delay. No one has found a room-temperature superconductor, and after decades of research there is not even a hint that one could exist. In all, there’s nothing better than a 15nm copper contact (see figure).

SEM cross section of 15-16 nm Cu contacts post-anneal. There is no Cu diffusion through the Ru to the silicide, and no void formation. (source: IBM)

Just over two years ago at IEDM 2007 in Washington, D.C., an evening panel discussed “Looking beyond silicon – a pipe dream or the inevitable next step?” While most of the discussion had focused upon so-called “More than Moore” devices (beyond silicon-based CMOS), one of the final conclusions was that interconnects appear to be our real limitation. “There is no new switch in sight,” said Wilfried Haensch, IBM senior research manager. “All candidates are either non-manufacturable or they can not be wired up.”

So, any proposed new nanodevice must outperform CMOS, and for the near-term must rely upon the same connections as available to standard silicon CMOS. As the International Technology Roadmap for Semiconductors (ITRS) 2009 edition’s Emerging Research Devices (ERD) section mentions on page 23, “An accelerator that is offered as a CMOS replacement should offer a performance improvement relative to its CMOS implementation of an order of magnitude.” To justify the R&D costs and integration risks, any new conductor technology would likewise probably have to provide an order of magnitude improvement in performance.

Christopher Case, ITRS Interconnect TWIG Chair (currently with Solid State Solutions), writes in the January 2010 issue of Future Fab (special ITRS issue) that Cu is expected to be our interconnect for at least the next 15 years. For any interconnect to complete with nanoscale copper contacts, Case reminds us that, “the goal is propagating terabits/second at femtojoules/bit.” He provides an excellent overview of the inherent challenges in trying to improve upon copper contacts.

As Case reminds us, from first principles of materials it seems that the only way to improve upon today’s copper contacts is to eliminate the internal grain boundaries that induce electron scattering. We can grow CNTs or single-crystal metal fibers from nanoscale catalyst dots, but we’re still only at the proof-of-concept stage. We’ve discovered graphene, but we’re still just beginning to learn about what we have yet to prove. If you attend the MRS Nanocontacts and Nanointerconnects Workshop in two weeks, you’ll probably learn the lower size limits of what we can build today and most of tomorrow.—E.K.