Posts Tagged ‘MPS’

Friday, January 7th, 2011

IEDM 2010 showed evolutions of NAND Flash with ALD IPD and ECC to 1Xnm node processing, and embedded-DRAM (eDRAM) capacitor stacks in porous low-k, meaning mainstream memory technologies will continue to dominate commercial volumes.

Friday, March 20th, 2009

Novellus’ applications labs have been working on CVD low-k dielectrics targeting 32nm node multilevel metal specs, and the result is “dense” ultra-low-k (ULK) film with bulk k=2.5 and the potential to go lower. Combined with the company’s multi-station sequential processing (MSSP) tool architecture for the barrier/cap depositions and UV/thermal cure steps, the result is a […]

Tuesday, March 17th, 2009

Breaking news about a leading porous low-k (PLK) material from Japan was first revealed in the SemiNeedle Planarization Lounge Forums (www.semineedle.com/forums/5001) about two months ago. During an expert panel discussion on CMP integration with low-k materials (moderated by this editor, summarized in “Chemical-Mechanical Planarization (CMP) technology consensus 09Q1” publication available at the site), Dick James, […]