Posts Tagged ‘dielectric’

Wednesday, August 25th, 2010

For 32nm and 22nm node ICs, Applied Materials’ FCVD and Novellus Systems’ CFD technologies provide gapfill, sidewall spacers, and conformal oxides for logic and NAND, plus SSDP litho.

Friday, May 1st, 2009

Leaving California for the first time, the 12th annual IEEE International Interconnect Technology Conference (IITC) will take place in Sapporo, Japan, June 1-3. With lithographic shrinks in 2D dimensions slowing, interconnects between chips in packages and in 3D stacks will be the driver for increased density and functionality in ICs. Thus, the more than 80 […]

Tuesday, March 17th, 2009

Breaking news about a leading porous low-k (PLK) material from Japan was first revealed in the SemiNeedle Planarization Lounge Forums (www.semineedle.com/forums/5001) about two months ago. During an expert panel discussion on CMP integration with low-k materials (moderated by this editor, summarized in ‚ÄúChemical-Mechanical Planarization (CMP) technology consensus 09Q1” publication available at the site), Dick James, […]