Posts Tagged ‘low-k’

Wednesday, June 16th, 2010

Intel shows vertical integration pays off with air-gaps through manufacturing cost reduction in low-k dielectrics for 32nm and 22nm node IC interconnects.

Friday, May 1st, 2009

Leaving California for the first time, the 12th annual IEEE International Interconnect Technology Conference (IITC) will take place in Sapporo, Japan, June 1-3. With lithographic shrinks in 2D dimensions slowing, interconnects between chips in packages and in 3D stacks will be the driver for increased density and functionality in ICs. Thus, the more than 80 […]

Monday, April 20th, 2009

The Materials Research Society (MRS) Spring Meeting in San Francisco is so huge, this year attracting a record of over 5,000 attendees, that strategy is needed to try to see any representative sample of the event. To provide in-depth information about new materials technologies, new symposia have been added over the years such that there […]

Thursday, April 2nd, 2009

The control of complex interdependencies is critical for the successful manufacturing of nanometer-scale ICs. Every aspect of every unit process step in the line must be ever more tightly controlled to ensure that 45nm and 32nm node chips can be made with good yield. To serve the market, Novellus continues to announce new integrated surface-treatment […]

Wednesday, April 1st, 2009

Asahi Glass is promoting a family of new photosensitive spin-on-dielectric (SOD) films for fan-out WLP and 3D packages, as well as for FPD and MEMS applications. The Chemicals Fluoroproducts Division of Asahi Glass has successfully developed the AL-X polymer series, primarily targeting the redistribution/rewiring layers in fan-out WLP packages. The company will begin production of […]

Friday, March 20th, 2009

Novellus’ applications labs have been working on CVD low-k dielectrics targeting 32nm node multilevel metal specs, and the result is “dense” ultra-low-k (ULK) film with bulk k=2.5 and the potential to go lower. Combined with the company’s multi-station sequential processing (MSSP) tool architecture for the barrier/cap depositions and UV/thermal cure steps, the result is a […]

Tuesday, March 17th, 2009

Breaking news about a leading porous low-k (PLK) material from Japan was first revealed in the SemiNeedle Planarization Lounge Forums ( about two months ago. During an expert panel discussion on CMP integration with low-k materials (moderated by this editor, summarized in “Chemical-Mechanical Planarization (CMP) technology consensus 09Q1” publication available at the site), Dick James, […]

Thursday, February 19th, 2009

JSR announced today that it has entered into several joint development partnerships (JDP) with IBM to develop low-k dielectrics for 32nm and 22nm nodes of semiconductor technology. The companies will work on next generation materials JSR has had in development and commercial production, including low-k dielectrics and a broad range of photoresists. “This larger scale […]