Posts Tagged ‘integration’

Monday, July 25th, 2011

Innovalight specialty PV materials company gets acquired by DuPont after successful integration of its silicon-ink screen-printed selective emitter (SE) into mulitple customer crystalline-silicon production lines.

Monday, November 8th, 2010

Xilinx 28nm FPGA Virtex-7 uses TSMC 65nm multi-level-metal (MLM) and through-silicon-via (TSV) Si-interposer for 2M gate and ARM-core integration product family.

Wednesday, August 25th, 2010

For 32nm and 22nm node ICs, Applied Materials’ FCVD and Novellus Systems’ CFD technologies provide gapfill, sidewall spacers, and conformal oxides for logic and NAND, plus SSDP litho.

Wednesday, June 16th, 2010

Intel shows vertical integration pays off with air-gaps through manufacturing cost reduction in low-k dielectrics for 32nm and 22nm node IC interconnects.

Friday, May 1st, 2009

Leaving California for the first time, the 12th annual IEEE International Interconnect Technology Conference (IITC) will take place in Sapporo, Japan, June 1-3. With lithographic shrinks in 2D dimensions slowing, interconnects between chips in packages and in 3D stacks will be the driver for increased density and functionality in ICs. Thus, the more than 80 […]

Monday, April 6th, 2009

Applied Materials and Disco announced a joint effort to develop wafer thinning processes for fabricating through-silicon vias (TSV) for future 3D IC stacks. The two companies, world leaders in thin-films and thinning (respectively) for silicon wafers, will be working together to develop integrated, high-performance process flows intended to lower the cost, reduce the risk and […]

Thursday, March 26th, 2009

German and French teams are combining EUR 14.5m investment into development of strained-silicon on insulator (sSOI) technology under the DEvice and CIrcuit performance boosted through SIlicon material Fabrication (DECISIF) program. The work will combine original research results from Research Center Juelich and Leti/Soitec to try to lower costs and defect-densities in the creation of 300mm […]

Friday, January 30th, 2009

Ziptronix wants to help you with your 3D roadmap. The IP spin-out from Research Triangle Park, NC is now actively negotiating licenses to its unique wafer-to-wafer (W2W) and die-to-wafer (D2W) bonding technologies. Using treated-oxide (with surface treatments) and nickel (with a mystery metal) as the connecting materials, room temperature bonding with up to 108/cm2 of […]

Wednesday, January 28th, 2009

Silicon Clocks, the developer of custom semiconductor timing solutions that has reinvented itself as a “custom product development house” with a new CEO, has announced a new product based on its CMOS-MEMS (CMEMS) embedded approach. CMEMS-ZeroThermal passive temperature compensation resonators exhibit comparable temperature stability to quartz crystals, while drastically simplifying oscillator design, and reportedly reducing […]

Wednesday, January 14th, 2009

Smart Equipment Technology (S.E.T.), a wholly-owned subsidiary of Replisaurus Technologies and a leading supplier of high accuracy die-to-die (D2D), die-to-wafer (D2W) bonding and nanoimprint lithography solutions, announced yesterday that it will collaborate with IMEC on 3DIC R&D. IMEC’s 3D integration program explores 3D technology and design for applications in various domains, focusing on 3D WLP […]