Posts Tagged ‘32nm’

Friday, January 7th, 2011

IEDM 2010 showed evolutions of NAND Flash with ALD IPD and ECC to 1Xnm node processing, and embedded-DRAM (eDRAM) capacitor stacks in porous low-k, meaning mainstream memory technologies will continue to dominate commercial volumes.

Monday, November 29th, 2010

Applied Materials lauches Centris platform for AdvantEdge MESA etch chambers, claiming 180 wph throughput, 0.8nm CD, and 30% lower CoO. Also releases new ultra HDP Silvia etch chamber for Centura, claiming $10 per wafer TSV etch.

Friday, November 26th, 2010

Qcept Technologies’ ChemitriQ5000 may help GlobalFoundries vs. TSMC in gate-first HKMG integration for 32nm foundry customers with fab metrology for control of yield excursions

Monday, November 8th, 2010

Xilinx 28nm FPGA Virtex-7 uses TSMC 65nm multi-level-metal (MLM) and through-silicon-via (TSV) Si-interposer for 2M gate and ARM-core integration product family.

Tuesday, September 14th, 2010

E-beam Initiative adds four members and starts on Design for E-beam (DFEB) for mask makng for ICs to reduce mask costs at 22nm and below.

Wednesday, August 25th, 2010

For 32nm and 22nm node ICs, Applied Materials’ FCVD and Novellus Systems’ CFD technologies provide gapfill, sidewall spacers, and conformal oxides for logic and NAND, plus SSDP litho.

Tuesday, August 17th, 2010

Post-optical lithography (NGL) technologies EUV (EUVL), e-beam direct-write (EbDW), and nano-imprint (NIL) all need work as shown at SEMICON/West 2010, major costs limitations.

Monday, July 19th, 2010

Soft plasmas for monolayer etching by Ed Korczynski at NCCAVS PAG meeting at SEMICON/West 2010, including TEL Tactras RLSA and AMAT AdvantEdge Mesa for HKMG 32nm, STI, and bWL etches.

Monday, July 5th, 2010

ALD/CVD systems for new materials R&D by Altatech Semiconductor sold to Fraunhofer IZM ASSID and ENAS for 3DIC and high mobility research using liquid injection of precursors.

Wednesday, June 16th, 2010

Intel shows vertical integration pays off with air-gaps through manufacturing cost reduction in low-k dielectrics for 32nm and 22nm node IC interconnects.