Posts Tagged ‘cost’

Tuesday, August 17th, 2010

Post-optical lithography (NGL) technologies EUV (EUVL), e-beam direct-write (EbDW), and nano-imprint (NIL) all need work as shown at SEMICON/West 2010, major costs limitations.

Tuesday, December 1st, 2009

Based on proven hardware sub-systems from previous models, Applied Materials has released a new chemical-mechanical planarization (CMP) tool that processes two 300mm diameter wafers simultaneously on each of two plattens. Initially targeting copper interconnect formation for memory ICs, the Reflexion GT tool has passed betasite tests at multiple customers, and reportedly provides 60% higher throughput […]

Friday, February 6th, 2009

The SEMI PV Group today announced the release of its Global Photovoltaic (PV) Standards Roadmap Guidance Document, which identifies immediate opportunities for reducing cost and accelerating innovation in thin-film and crystalline silicon cell and module manufacturing through industry standards. This new roadmap confirms that major manufacturing cost savings are possible through standardizing wafer carriers and […]