Posts Tagged ‘32nm’

Monday, March 15th, 2010

Another back-to-the-future possibility for next-generation lithography (NGL) is direct write e-beam (DWEB), revitalized with multibeam clusters, curvilinear mask writing, and character projection (CP). The E-beam Initiative used the recent SPIE gathering to announce that it had added six new member companies, including GlobalFoundries and Samsung. Aki Fujimura, CEO of D2S and Managing Director of the […]

Monday, March 8th, 2010

This year’s plenary sessions of the SPIE Advanced Lithography Symposium exposed the complexities of patterning ICs in high-volume manufacturing (HVM) at the 22nm node and beyond. Steppers using 193nm ArF immersion (193i) will be extended using double-patterning (DP) schemes, since the extreme-ultra-violet litho (EUVL) infrastructure is again delayed. R&D to support DP integration has led […]

Thursday, October 22nd, 2009

If EUV lithography is to succeed, infrastructure gaps will need to be addressed forthwith. The lack of inspection tools for EUV masks and substrates constitutes one such gap, now recognized as a priority by SEMATECH. At the OSA/APS Frontiers in Optics (FiO) meeting held in San Jose, October 11-15, Carmen Menoni of Colorado State University […]

Friday, October 9th, 2009

Founded in 1984 with Flemish government support, IMEC has reached 25 years. To celebrate the organization’s accomplishments, BetaSights joined other industry media outlets attending a research review event in beautiful Leuven, Belgium. From 1999 to 2009 has been the “phase of international breakthrough” as described by current president Luc Van den hove. Working with OEMs […]

Sunday, October 4th, 2009

KLA-Tencor recently announced its long awaited 193nm reticle defect inspection tool, the Teron 600. Wafer scanners adopted 193nm exposure wavelength years ago in order to shrink circuit features below the resolution limit set by the previous (248nm) wavelength, roughly 130nm. The photomasks used in those tools, however, continued to be inspected at 257nm, in spite […]

Friday, September 18th, 2009

At SEMICON West this year, ASML announced tools that fleshed out their Holistic Lithography scheme introduced at SPIE’s Advanced Lithography Symposium in February of this year. The key idea of Holistic Lithography, according to Bert Koek, senior vice president of the applications products group at ASML, is integrating computational lithography, wafer printing, and process control […]

Monday, August 17th, 2009

Luminescent Technologies, Inc., a computational lithography company, has broadened its reach by announcing the industry’s first offline computational photomask inspection product (unofficially named LAIPH for Luminescent Automated Image Processing Hub). A “premier company in Asia” is the first customer to qualify the new computational defect review product in volume production. According to a Luminescent representative, […]

Wednesday, August 12th, 2009

At the SEMICON West 2009 Device Scaling TechXPOT, moderated by this editor, SEMATECH’s Ray Jammy reviewed the latest results in scaling CMOS transistors. “We are litererally running out of atoms,” explained Jammy. “You can see the number of atoms in a gate dielectric.” When you have such thin layers, how do you control device parameters? […]

Wednesday, July 22nd, 2009

At SEMICON West and Intersolar North America last week in San Francisco, crossing guards danced to keep the throngs away from the vehicles at the corner of 4th and Howard, as many people flowed back and forth between the shows co-located across 4th Street from each other. SEMICON West, down ~30% in size from last […]

Tuesday, July 7th, 2009

Applied Materials has extended physical vapor deposition (PVD) technology to be able to coat the sidewalls of 22nm node structures. “It’s been validated, it’s been shipped, and it’s been qualified in pilot lines for both logic and memory,” asserted Marek Radko, Applied Materials’ BEOL GPM Manager, in an exclusive interview with BetaSights. Separately, the company […]