Posts Tagged ‘32nm’

Wednesday, March 4th, 2009

Electron beam direct write (EBDW) lithography is well-developed and has better potential resolution than any other method, but writing speeds did not keep up with Moore’s law after about 1980, leading to abysmal throughput (measured in hours per wafer). Now, the e-Beam Initiative focusing on design for e-beam manufacturing (DFEB) and multibeam writing using MEMS […]

Monday, March 2nd, 2009

Partners SII NanoTechnology and Carl Zeiss NTS have joined with ASML R&D and Toshiba’s process and manufacturing engineering groups to show a new way to create accurate cross-sections of soft photoresist and low-k dielectric lines in dense circuit patterns. First shown in a poster paper at SPIE last week was the ability to generate accurate […]

Thursday, February 26th, 2009

One year after this editor covered an SPIE panel on reference metrology and summarized the situation as “there is no more noise; there is only signal,” another lively panel at SPIE this evening discussed the need for not just precise but accurate critical dimension (CD) measurements in advanced IC lines. With smaller structures and reduced […]

Monday, February 23rd, 2009

JEOL will install the first e-beam direct-write-on-wafer (EBDW) lithography tool to support nanotechnology development in the Pacific Northwest when the University of Washington takes delivery of a JBX-6300FS tool. The system will be installed in the state-funded Washington Technology Center Microfabrication Lab. Funding for the tool acquisition was provided through a state-supported STAR researchers’ grant […]

Thursday, February 19th, 2009

JSR announced today that it has entered into several joint development partnerships (JDP) with IBM to develop low-k dielectrics for 32nm and 22nm nodes of semiconductor technology. The companies will work on next generation materials JSR has had in development and commercial production, including low-k dielectrics and a broad range of photoresists. “This larger scale […]

Monday, January 26th, 2009

CEA/Leti, along with e-beam lithography supplier Vistec, and new design and software company D2S, recently announced a collaboration focused on refining and validating advanced design-for-e-beam (DFEB) solutions for 45nm and 32nm nodes. Over the next 12 months, Leti will manufacture test chips using a combination of D2S’ design and software capabilities along with the latest […]

Tuesday, January 13th, 2009

At SEMI’s Industry Strategy Symposium (ISS) running at Half Moon Bay, California today, IMEC president and CEO Gilbert Declerck talked about the need for R&D to facilitate IC industry growth. An industry based on answering the question, “what have you done for me lately?” can never rest on past successes and must continue to innovate. […]

Wednesday, January 7th, 2009

On January 6, 2009, ASM International and SAFC Hitech (a business segment within SAFC, a member of the Sigma-Aldrich Group) announced that they have entered into a certified manufacturer and partnership agreement for ALD precursors for barium- and strontium-based high-k insulators.  The agreement includes certification criteria, a license to certain ASM ALD patents, and a […]

Monday, January 5th, 2009

FSI International, Inc. (Nasdaq: FSII) announced December 23, 2008 that it has received an order for it’s new ORION® single wafer cleaning platform after a beta evaluation by a major semiconductor manufacturer. The tool will be used for resist strip in 32nm metal interconnect modules, using FSI’s proprietary “ViPR” extension of the classic “piranha” (a.k.a., […]