Posts Tagged ‘litho’

Wednesday, April 1st, 2009

Asahi Glass is promoting a family of new photosensitive spin-on-dielectric (SOD) films for fan-out WLP and 3D packages, as well as for FPD and MEMS applications. The Chemicals Fluoroproducts Division of Asahi Glass has successfully developed the AL-X polymer series, primarily targeting the redistribution/rewiring layers in fan-out WLP packages. The company will begin production of […]

Wednesday, March 4th, 2009

Electron beam direct write (EBDW) lithography is well-developed and has better potential resolution than any other method, but writing speeds did not keep up with Moore’s law after about 1980, leading to abysmal throughput (measured in hours per wafer). Now, the e-Beam Initiative focusing on design for e-beam manufacturing (DFEB) and multibeam writing using MEMS […]

Wednesday, February 25th, 2009

Applied Materials’ Technical Symposium at SPIE 2009 featured a panel discussion on next generation lithography (NGL) that was moderated by the company’s Ken MacWIlliams. The outstanding panelists were C. Grant Willson (UT-Austin), Burn Lin (TSMC), Jongwook Kye (AMD), Steve Radigan (Sandisk), and Milind Weling (Cadence). As would be expected from this panel, EUV steppers were […]

Tuesday, February 24th, 2009

At the Nikon Lithovisions 2009 Symposium on February 22 this year in San Jose, California, Masato Hamatani described the features and beta test results for the NSR-S620 scanning immersion exposure tool, optimized for double patterning lithography. While the tool boasts only one wafer stage, its “Streamlign Platform” concept shoots 200 wafers per hour with 2nm […]

Friday, February 20th, 2009

As computational lithography has become big big business, the pioneering enterprises have been assimilated into larger organizations (KLA-Tencor for Finle and Synopsys for Sigma-C, to name two examples). Panoramic Technology, however, continues its independence, supplying trustworthy and up-to-date simulators to advanced lithographers for a decade. Past Panoramic products, however, employed an interface that was familiar […]

Thursday, February 19th, 2009

JSR announced today that it has entered into several joint development partnerships (JDP) with IBM to develop low-k dielectrics for 32nm and 22nm nodes of semiconductor technology. The companies will work on next generation materials JSR has had in development and commercial production, including low-k dielectrics and a broad range of photoresists. “This larger scale […]

Wednesday, February 18th, 2009

For thick plating applications like copper pillar bump processing in semiconductor advanced packaging, Shin-Etsu MicroSi has introduced a positive tone, ultra-thick photoresist, SIPR-7126. The 7100 chemically amplified (CA) series has been in production for several years, and the SIPR-7126 has been optimized to reduce processing steps and improve removability in layers up to 100 µm […]