Archive for the ‘Equipment’ Category

Tuesday, September 14th, 2010

E-beam Initiative adds four members and starts on Design for E-beam (DFEB) for mask makng for ICs to reduce mask costs at 22nm and below.

Tuesday, September 7th, 2010

HP and Hynix JVA for ReRAM chips, based on HP titania memristor as covered by BetaSights April 2010, with R&D fab in Korea to start work on integration on 300mm silicon wafers for 2013 IC chips

Wednesday, August 25th, 2010

For 32nm and 22nm node ICs, Applied Materials’ FCVD and Novellus Systems’ CFD technologies provide gapfill, sidewall spacers, and conformal oxides for logic and NAND, plus SSDP litho.

Tuesday, August 17th, 2010

Post-optical lithography (NGL) technologies EUV (EUVL), e-beam direct-write (EbDW), and nano-imprint (NIL) all need work as shown at SEMICON/West 2010, major costs limitations.

Thursday, August 5th, 2010

SEMICON/West 2010 lithography changes were slight, TEL showed quadruple-patterning with ALD sidewall spacers and tools, Nikon and ASML with IMEC also showed double-patterning

Wednesday, July 21st, 2010

Applied Materials kills the turnkey SunFab thin-film a-Si/mc-Si PV line, after failing to keep up with CdTe and CIGS thin-film technologies in efficiency and cost, taking ~$400M loss.

Monday, July 19th, 2010

Soft plasmas for monolayer etching by Ed Korczynski at NCCAVS PAG meeting at SEMICON/West 2010, including TEL Tactras RLSA and AMAT AdvantEdge Mesa for HKMG 32nm, STI, and bWL etches.

Monday, July 5th, 2010

ALD/CVD systems for new materials R&D by Altatech Semiconductor sold to Fraunhofer IZM ASSID and ENAS for 3DIC and high mobility research using liquid injection of precursors.

Thursday, April 22nd, 2010

HP Labs in Palo Alto has been leading the development of the “memristor,” and researchers there have finally discovered the underlying mechanism for the formation of devices that can function as memory cells, logic circuits, and potentially even real artificial intelligence (AI)! Disclosing these results in his plenary speech to the attendees at the Nanocontacts […]

Monday, April 5th, 2010

The 2010 SPIE Advanced Lithography conference is where we first get glimpses of the future of nano-scale patterning technology for manufacturing. Sometimes, many fuzzy blobs come into focus as a picture in a single moment, and Yan Borodovsky of Intel showed how to do 22nm node litho the day before SPIE officially started. At both […]